Author: tstellar
Date: Mon Nov 9 10:25:06 2015
New Revision: 252479
URL: http://llvm.org/viewvc/llvm-project?rev=252479&view=rev
Log:
Merging r246675:
------------------------------------------------------------------------
r246675 | hfinkel | 2015-09-02 12:52:37 -0400 (Wed, 02 Sep 2015) | 9 lines
[PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLE
LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the
TableGen-generated matching code, and it does this by testing the same
predicates used by the TableGen files. Unfortunately, when we added new
P8Altivec-only predicates, we started universally testing them in
LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8,
we'd end up with a selection failure.
------------------------------------------------------------------------
Added:
llvm/branches/release_37/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
Modified:
llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp
Modified: llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp?rev=252479&r1=252478&r2=252479&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/PPCISelLowering.cpp Mon Nov 9
10:25:06 2015
@@ -7177,7 +7177,6 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isSplatShuffleMask(SVOp, 4) ||
PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
- PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
@@ -7185,8 +7184,10 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
+ (Subtarget.hasP8Altivec() && (
+ PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
return Op;
}
}
@@ -7197,7 +7198,6 @@ SDValue PPCTargetLowering::LowerVECTOR_S
unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
- PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
@@ -7205,8 +7205,10 @@ SDValue PPCTargetLowering::LowerVECTOR_S
PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
- PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
+ (Subtarget.hasP8Altivec() && (
+ PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
+ PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
return Op;
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
Added: llvm/branches/release_37/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll?rev=252479&view=auto
==============================================================================
--- llvm/branches/release_37/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
(added)
+++ llvm/branches/release_37/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
Mon Nov 9 10:25:06 2015
@@ -0,0 +1,28 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
+entry:
+ %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32>
<i32 0, i32 2>
+ ret <2 x i32> %strided.vec
+
+; CHECK-LABEL: @test1
+; CHECK: vsldoi 2, 2, 2, 12
+; CHECK: blr
+}
+
+; Function Attrs: nounwind
+define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
+entry:
+ %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x
i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3,
i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
+ ret <16 x i8> %strided.vec
+
+; CHECK-LABEL: @test2
+; CHECK: vsldoi 2, 2, 2, 12
+; CHECK: blr
+}
+
+attributes #0 = { nounwind "target-cpu"="pwr7" }
+
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