Author: tstellar
Date: Mon Nov 9 10:25:01 2015
New Revision: 252477
URL: http://llvm.org/viewvc/llvm-project?rev=252477&view=rev
Log:
Merging r246372:
------------------------------------------------------------------------
r246372 | hfinkel | 2015-08-30 03:44:05 -0400 (Sun, 30 Aug 2015) | 10 lines
[PowerPC] Don't assume ADDISdtprelHA's source is r3
Even through ADDISdtprelHA generally has r3 as its source register, it is
possible for the instruction scheduler to move things around such that some
other register is the source. We need to print the actual source register, not
always r3. Fixes PR24394.
The test case will come in a follow-up commit because it depends on MIR
target-flags parsing.
------------------------------------------------------------------------
Modified:
llvm/branches/release_37/lib/Target/PowerPC/PPCAsmPrinter.cpp
Modified: llvm/branches/release_37/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=252477&r1=252476&r2=252477&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Nov 9
10:25:01 2015
@@ -947,11 +947,11 @@ void PPCAsmPrinter::EmitInstruction(cons
return;
}
case PPC::ADDISdtprelHA:
- // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
- // Into: %Xd = ADDIS8 %X3, sym@dtprel@ha
+ // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym>
+ // Into: %Xd = ADDIS8 %Xs, sym@dtprel@ha
case PPC::ADDISdtprelHA32: {
- // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
- // Into: %Rd = ADDIS %R3, sym@dtprel@ha
+ // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym>
+ // Into: %Rd = ADDIS %Rs, sym@dtprel@ha
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
@@ -962,7 +962,7 @@ void PPCAsmPrinter::EmitInstruction(cons
*OutStreamer,
MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS)
.addReg(MI->getOperand(0).getReg())
- .addReg(Subtarget->isPPC64() ? PPC::X3 : PPC::R3)
+ .addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
return;
}
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