================
@@ -736,6 +742,26 @@ multiclass si_cs_chain_tc_patterns<
defm : si_cs_chain_tc_patterns<i32>;
defm : si_cs_chain_tc_patterns<i64>;
+// Match dynamic VGPR case. This is always indirect since we choose the callee
+// dynamically based on the result of the VGPR reallocation, so make sure to
+// drop the callee info if there is any.
+multiclass si_cs_chain_tc_dvgpr_patterns<
+ ValueType execvt, RegisterOperand execrc = getSOPSrcForVT<execvt>.ret,
+ Instruction tc = SI_CS_CHAIN_TC_W32_DVGPR> {
+ let AddedComplexity = 90 in {
----------------
rovka wrote:
To be honest, I wrote this >1 year ago, so I don't really remember why I chose
to do it this way. I reworked it to use a different ISD node for dynamic VGPRs,
I hope it's cleaner this way.
https://github.com/llvm/llvm-project/pull/130094
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