[llvm-branch-commits] [llvm] [LV] Reduce register usage for scaled reductions (PR #133090)

[Sam Tebbs via llvm-branch-commits]

================
@@ -5026,10 +5026,24 @@ calculateRegisterUsage(VPlan &Plan, 
ArrayRef<ElementCount> VFs,
             // even in the scalar case.
             RegUsage[ClassID] += 1;
           } else {
+            // The output from scaled phis and scaled reductions actually have
+            // fewer lanes than the VF.
+            auto VF = VFs[J];
----------------
SamTebbs33 wrote:

Done.

https://github.com/llvm/llvm-project/pull/133090
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