================
@@ -303,4 +303,10 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
(SUBrr (UMULXHI $lhs, $rhs),
(ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
(ANDrr (SRAXri $rhs, 63), $lhs)))>;
+
+def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
+// 32-bit LZCNT.
+// The zero extension will leave us with 32 extra leading zeros,
+// so we need to compensate for it.
+def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
----------------
koachan wrote:
I'm sorry, I just noticed something.
The instruction should still work on 32-bit V8+ target, and `Promote`-ing
doesn't work there at the moment.
Since the V8+ targets have 64-bit physical registers anyway, the subsequent
subtraction would still be safe, so I think I'll keep the pattern for now, at
least until the codegen supports using the full width of the registers.
https://github.com/llvm/llvm-project/pull/135715
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
