llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: Koakuma (koachan) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/138400.diff 5 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+9-4) - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+5) - (added) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+21) - (added) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+6) - (added) llvm/test/MC/Sparc/sparc-ua2005.s (+8) ``````````diff diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 2083c0e763b82..0d66a03fd941d 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -49,6 +49,9 @@ def FeatureVIS2 def FeatureVIS3 : SubtargetFeature<"vis3", "IsVIS3", "true", "Enable Visual Instruction Set extensions III">; +def FeatureUA2005 + : SubtargetFeature<"ua2005", "IsUA2005", "true", + "Enable UltraSPARC Architecture 2005 extensions">; def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; @@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; // LEON 2 FT generic def : Processor<"leon2", LEON2Itineraries, diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 0c890721da0f4..a220e0379213c 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">, def HasVIS3 : Predicate<"Subtarget->isVIS3()">, AssemblerPredicate<(all_of FeatureVIS3)>; +// HasUA2005 - This is true when the target processor has UA 2005 extensions. +def HasUA2005 : Predicate<"Subtarget->isUA2005()">, + AssemblerPredicate<(all_of FeatureUA2005)>; + // HasHardQuad - This is true when the target processor supports quad floating // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; @@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), include "SparcInstr64Bit.td" include "SparcInstrVIS.td" +include "SparcInstrUAOSA.td" include "SparcInstrAliases.td" diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td new file mode 100644 index 0000000000000..d883e517db89d --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -0,0 +1,21 @@ +//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction formats, definitions and patterns needed for +// UA 2005 instructions on SPARC. +//===----------------------------------------------------------------------===// + +// UltraSPARC Architecture 2005 Instructions +let Predicates = [HasUA2005] in { +let hasSideEffects = 1 in +def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { + let op = 2; + let Inst{29-19} = 0b00010110001; + let Inst{18-0} = 0; +} +} // Predicates = [HasUA2005] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt new file mode 100644 index 0000000000000..dc3d196091c6b --- /dev/null +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s + +## UA 2005 instructions. + +# CHECK: allclean +0x85,0x88,0x00,0x00 diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s new file mode 100644 index 0000000000000..2214b91b335cd --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-ua2005.s @@ -0,0 +1,8 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005 + +!! UA 2005 instructions. + +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00] +allclean `````````` </details> https://github.com/llvm/llvm-project/pull/138400 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
