[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (PR #132382)

[Pierre van Houtryve via llvm-branch-commits]

================
@@ -237,6 +237,21 @@ void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
   MI.eraseFromParent();
 }
 
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
----------------
Pierre-vh wrote:

```suggestion
  LLT Ty = (MRI.getType(Dst) == V4S16 ? V2S16 : S32);
```

nit for clarity; are you also expecting the type of be something else 
specifically if it isn't `V4S16` ? If so I'd add an assert to avoid silent 
failures

https://github.com/llvm/llvm-project/pull/132382
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