[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (PR #132382)

[Matt Arsenault via llvm-branch-commits]

================
@@ -231,6 +232,23 @@ void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
   MI.eraseFromParent();
 }
 
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  assert(DstTy == V4S16 || DstTy == V2S32 || DstTy == S64);
+  LLT Ty = (DstTy == V4S16 ? V2S16 : S32);
----------------
arsenm wrote:

```suggestion
  LLT Ty = DstTy == V4S16 ? V2S16 : S32;
```

https://github.com/llvm/llvm-project/pull/132382
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