https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/138400
>From b2e8de55ea9e54239a017eb932f7107f29f465a4 Mon Sep 17 00:00:00 2001 From: Koakuma <koac...@protonmail.com> Date: Sun, 4 May 2025 08:57:07 +0700 Subject: [PATCH 1/2] Add other instructions & fix typo Created using spr 1.3.5 --- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 17 ++++++++++++++++- .../test/MC/Disassembler/Sparc/sparc-ua-osa.txt | 6 ++++++ llvm/test/MC/Sparc/sparc-ua2005.s | 9 +++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td index d883e517db89d..5ecc02ed10bfb 100644 --- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -1,4 +1,4 @@ -//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// +//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -18,4 +18,19 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { let Inst{29-19} = 0b00010110001; let Inst{18-0} = 0; } +def INVALW : InstSP<(outs), (ins), "invalw", []> { + let op = 2; + let Inst{29-19} = 0b00101110001; + let Inst{18-0} = 0; +} +def NORMALW : InstSP<(outs), (ins), "normalw", []> { + let op = 2; + let Inst{29-19} = 0b00100110001; + let Inst{18-0} = 0; +} +def OTHERW : InstSP<(outs), (ins), "otherw", []> { + let op = 2; + let Inst{29-19} = 0b00011110001; + let Inst{18-0} = 0; +} } // Predicates = [HasUA2005] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt index dc3d196091c6b..4a2de98e03fe3 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -4,3 +4,9 @@ # CHECK: allclean 0x85,0x88,0x00,0x00 +# CHECK: invalw +0x8b,0x88,0x00,0x00 +# CHECK: otherw +0x87,0x88,0x00,0x00 +# CHECK: normalw +0x89,0x88,0x00,0x00 diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s index 2214b91b335cd..b07c99a20033b 100644 --- a/llvm/test/MC/Sparc/sparc-ua2005.s +++ b/llvm/test/MC/Sparc/sparc-ua2005.s @@ -6,3 +6,12 @@ ! NO-UA2005: error: instruction requires a CPU feature not currently enabled ! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00] allclean +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: invalw ! encoding: [0x8b,0x88,0x00,0x00] +invalw +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: otherw ! encoding: [0x87,0x88,0x00,0x00] +otherw +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: normalw ! encoding: [0x89,0x88,0x00,0x00] +normalw >From a2c49c5b9ecf2451a20d660cdc059c3301a8b816 Mon Sep 17 00:00:00 2001 From: Koakuma <koac...@protonmail.com> Date: Mon, 12 May 2025 07:26:35 +0700 Subject: [PATCH 2/2] Fix indentation Created using spr 1.3.5 --- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td index 8a833636301d0..b00995a960968 100644 --- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -12,9 +12,9 @@ class UA2005RegWin<string asmstr, bits<5> fcn> : F3_1<2, 0b110001, (outs), (ins), asmstr, []> { - let rd = fcn; - let rs1 = 0; - let rs2 = 0; + let rd = fcn; + let rs1 = 0; + let rs2 = 0; } // UltraSPARC Architecture 2005 Instructions _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
