https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161801
SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make sense. >From 04a448a4f8da85d879ffb61618a824bd2ab5a62a Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 3 Oct 2025 15:53:00 +0900 Subject: [PATCH] AMDGPU: Stop using the wavemask register class for SCC cross class copies SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make sense. --- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 21735f91f4ad7..ba29dd4ae61d4 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const { const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { - if (RC == &AMDGPU::SCC_CLASSRegClass) - return getWaveMaskRegClass(); - return RC; + return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC; } static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI, _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
