================
@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const {
const TargetRegisterClass *
SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- if (RC == &AMDGPU::SCC_CLASSRegClass)
- return getWaveMaskRegClass();
- return RC;
+ return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;
----------------
arsenm wrote:
No. These have nothing to do with each other. To extract a value into an
allocatable register, a 32-bit SGPR is the natural choice
https://github.com/llvm/llvm-project/pull/161801
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