https://github.com/gbossu updated https://github.com/llvm/llvm-project/pull/173005
From 219565ced40970ffa12b4d88bb90552245d5575d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <[email protected]> Date: Fri, 19 Dec 2025 13:10:56 +0000 Subject: [PATCH] [AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 +++++++++++ llvm/test/CodeGen/AArch64/sve-insert-element.ll | 16 ++-------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 837393b0cbdcd..8c56071c5527d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -27792,6 +27792,17 @@ performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { if (SDValue Res = removeRedundantInsertVectorElt(N)) return Res; + // Turn INSERT_VECTOR_ELT(undef, Elt, Idx) into SPLAT_VECTOR(Elt) + // Do not bother with inserts into lane 0 because there are patterns to select + // them using INSERT_SUBREG hsub/ssub/dsub. + SDLoc DL(N); + SDValue Vec = N->getOperand(0); + SDValue Elt = N->getOperand(1); + SDValue Idx = N->getOperand(2); + EVT VecVT = Vec.getValueType(); + if (VecVT.isScalableVector() && Vec->isUndef() && !isNullConstant(Idx)) + return DCI.DAG.getNode(ISD::SPLAT_VECTOR, DL, VecVT, Elt); + return performPostLD1Combine(N, DCI, true); } diff --git a/llvm/test/CodeGen/AArch64/sve-insert-element.ll b/llvm/test/CodeGen/AArch64/sve-insert-element.ll index a897850c1365d..0962fca96dbf5 100644 --- a/llvm/test/CodeGen/AArch64/sve-insert-element.ll +++ b/llvm/test/CodeGen/AArch64/sve-insert-element.ll @@ -165,7 +165,6 @@ define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) { ret <vscale x 16 x i8> %b } -; TODO: Implement DAG combiner. ; Test the INSERT_VECTOR_ELT(poison, ...) -> VECTOR_SPLAT combiner ; <vscale x 16 x i8> is used as a proxy for testing using IR, but the combiner ; is agnostic of the element type. @@ -173,12 +172,7 @@ define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) { define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) { ; CHECK-LABEL: test_lanex_16xi8_poison: ; CHECK: // %bb.0: -; CHECK-NEXT: index z0.b, #0, #1 -; CHECK-NEXT: mov w8, w1 -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov z1.b, w8 -; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b -; CHECK-NEXT: mov z0.b, p0/m, w0 +; CHECK-NEXT: mov z0.b, w0 ; CHECK-NEXT: ret %b = insertelement <vscale x 16 x i8> poison, i8 %e, i32 %x ret <vscale x 16 x i8> %b @@ -187,13 +181,7 @@ define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) { define <vscale x 16 x i8> @test_lanex_16xi8_poison_imm(i8 %e, i32 %x) { ; CHECK-LABEL: test_lanex_16xi8_poison_imm: ; CHECK: // %bb.0: -; CHECK-NEXT: index z0.b, #0, #1 -; CHECK-NEXT: mov w8, w1 -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov z1.b, w8 -; CHECK-NEXT: mov w8, #5 // =0x5 -; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b -; CHECK-NEXT: mov z0.b, p0/m, w8 +; CHECK-NEXT: mov z0.b, #5 // =0x5 ; CHECK-NEXT: ret %b = insertelement <vscale x 16 x i8> poison, i8 5, i32 %x ret <vscale x 16 x i8> %b _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
