https://github.com/petar-avramovic commented:
This should be generic combine, but we need target specific known bits
implementation for G_AMDGPU_COPY_SCC_VCC, assuming it would be safe to say that
G_AMDGPU_COPY_SCC_VCC defines low bit, and high bits are 0
%3:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC %2
%4:sgpr(s32) = G_CONSTANT i32 1
%5:sgpr(s32) = G_AND %3, %4
->
%5:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC %2
Think that what we are looking into is much more generic combine,
We are considering moving instruction to VALU if some of the inputs are coming
from readanylane or copy_scc_vcc
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
%3:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC %2
%8:sgpr(s32) = G_SELECT %5, %sgpr_x, %sgpr_y
%9:vgpr(s32) = COPY %8
->
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
%9:vgpr(s32) = G_SELECT %2, %sgpr_x, %sgpr_y
But select is a good start.
So can you check if known bits can be defined for G_AMDGPU_COPY_SCC_VCC, if too
complex can leave it for later
https://github.com/llvm/llvm-project/pull/179352
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