================
@@ -478,6 +486,65 @@ bool AMDGPURegBankCombinerImpl::applyD16Load(
return true;
}
+// Eliminate VCC->SGPR->VGPR register bounce for uniform boolean extensions.
+// Match: COPY (G_SELECT (G_AND (G_AMDGPU_COPY_SCC_VCC %vcc), 1), {-1|1}, 0)
+// Replace with: G_SELECT %vcc, {-1|1}, 0
+bool AMDGPURegBankCombinerImpl::matchCopySccVcc(
+ MachineInstr &MI, CopySccVccMatchInfo &MatchInfo) const {
+ assert(MI.getOpcode() == AMDGPU::COPY);
+
+ Register VgprDst = MI.getOperand(0).getReg();
+ Register SgprSrc = MI.getOperand(1).getReg();
+
+ if (!VgprDst.isVirtual() || !SgprSrc.isVirtual())
+ return false;
+
+ if (!isVgprRegBank(VgprDst))
+ return false;
+
+ // Match: G_SELECT (G_AND (G_AMDGPU_COPY_SCC_VCC %vcc), 1), TrueReg, 0
+ MachineInstr *CopySccVcc;
+ Register TrueReg;
+ if (!mi_match(SgprSrc, MRI,
+ m_GISelect(m_GAnd(m_MInstr(CopySccVcc), m_SpecificICst(1)),
----------------
petar-avramovic wrote:
think that there is no need to try and match constants in select, just match
the m_Reg. It might cover more cases
https://github.com/llvm/llvm-project/pull/179352
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