https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/180387
PR #156602 changed the condition for using 64-bit literal encoding, but it didn't update the instruction size calculation. This caused a size mismatch between the `MachineInstr` and the `MCInst`. >From ef972b95dd32ca553da7d1a160933b80306d3872 Mon Sep 17 00:00:00 2001 From: Shilei Tian <[email protected]> Date: Sat, 7 Feb 2026 22:41:01 -0500 Subject: [PATCH] [AMDGPU] Fix instruction size for 64-bit literal constant operands PR #156602 changed the condition for using 64-bit literal encoding, but it didn't update the instruction size calculation. This caused a size mismatch between the `MachineInstr` and the `MCInst`. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 9 ++++++++- .../AMDGPU/branch-relaxation-inst-size-gfx1250.mir | 12 ++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 9211de81b5fbf..1f5d9a3da1e0e 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -9791,7 +9791,14 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { LiteralSize = 8; break; case AMDGPU::OPERAND_REG_IMM_INT64: - if (!Op.isImm() || !AMDGPU::isValid32BitLiteral(Op.getImm(), false)) + // A 32-bit literal is only valid when the value fits in BOTH signed + // and unsigned 32-bit ranges [0, 2^31-1], matching the MC code + // emitter's getLit64Encoding logic. This is because of the lack of + // abilility to tell signedness of the literal, therefore we need to + // be conservative and assume values outside this range require a + // 64-bit literal encoding (8 bytes). + if (!Op.isImm() || !isInt<32>(Op.getImm()) || + !isUInt<32>(Op.getImm())) LiteralSize = 8; break; } diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir index 59c19f354ce54..ebc7253cf2027 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir @@ -30,11 +30,19 @@ machineFunctionInfo: body: | ; CHECK-LABEL: name: s_mov_b64_64bit_literal_size ; CHECK: bb.0: - ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc - ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc + ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sgpr4_sgpr5 = S_GETPC_B64 post-instr-symbol <mcsymbol > + ; CHECK-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc + ; CHECK-NEXT: $sgpr5 = S_ADDC_U32 $sgpr5, target-flags(<unknown target flag>) <mcsymbol >, implicit-def $scc, implicit $scc + ; CHECK-NEXT: S_SETPC_B64 $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
