https://github.com/el-ev created https://github.com/llvm/llvm-project/pull/196785
None >From 777dbd329c2b0a052b9fa08896a306fbafb556d2 Mon Sep 17 00:00:00 2001 From: Iris Shi <[email protected]> Date: Sun, 10 May 2026 15:09:16 +0800 Subject: [PATCH] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ---- llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 5dd025f1b42be..87dfa2f5a1c50 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) { AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT()) return N0; + // fold (assert?ext c, vt) -> c + if (isa<ConstantSDNode>(N0)) + return N0; + if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && N0.getOperand(0).getOpcode() == Opcode) { // We have an assert, truncate, assert sandwich. Make one stronger assert diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 894f04bb4668d..c001f0e0bd450 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -10853,10 +10853,6 @@ SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped()) return Op; - APInt Lo = CR->getUnsignedMin(); - if (!Lo.isMinValue()) - return Op; - APInt Hi = CR->getUnsignedMax(); unsigned Bits = std::max(Hi.getActiveBits(), static_cast<unsigned>(IntegerType::MIN_INT_BITS)); diff --git a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll index ad26dfa7f93e8..a8be7e5827af0 100644 --- a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll +++ b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll @@ -11,7 +11,7 @@ define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) % ; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 +; CHECK-NEXT: v_mov_b32_e32 v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: s_setpc_b64 s[30:31] %xor = xor i64 %arg0, %arg1 @@ -24,7 +24,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %a ; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_or_b32_e32 v1, v1, v3 +; CHECK-NEXT: v_mov_b32_e32 v1, v3 ; CHECK-NEXT: v_or_b32_e32 v0, v0, v2 ; CHECK-NEXT: s_setpc_b64 s[30:31] %or = or i64 %arg0, %arg1 @@ -50,7 +50,7 @@ define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64 0, 65) inreg %arg) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_not_b64 s[4:5], s[16:17] ; CHECK-NEXT: v_mov_b32_e32 v0, s4 -; CHECK-NEXT: v_mov_b32_e32 v1, s5 +; CHECK-NEXT: v_mov_b32_e32 v1, -1 ; CHECK-NEXT: s_setpc_b64 s[30:31] %xor = xor i64 %arg, -1 ret i64 %xor _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
