https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/208812
Continue migrating command-line target spelling on RUN lines to the folded amdgpu subarch triple form, covering the remaining Transforms tests in this group. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 205a4cf05a46302d5a9ca24cde18af98986b9f73 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 09:52:26 +0200 Subject: [PATCH] AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (4) Continue migrating command-line target spelling on RUN lines to the folded amdgpu subarch triple form, covering the remaining Transforms tests in this group. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll | 6 +++--- llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll | 6 +++--- .../AMDGPU/address-space-ptr-sze-gep-index-assert.ll | 2 +- .../Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll | 6 +++--- llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll | 6 +++--- .../SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll | 2 +- .../Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll | 2 +- .../SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll | 2 +- llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll | 6 +++--- llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll | 4 ++-- .../Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll | 2 +- llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll | 4 ++-- .../Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll | 6 +++--- llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll | 6 +++--- llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll | 4 ++-- llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll | 4 ++-- llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll | 4 ++-- .../SLPVectorizer/AMDGPU/transform-node-gather-struct.ll | 2 +- .../SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll | 2 +- .../SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll | 4 ++-- .../SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll | 2 +- .../AMDGPU/nontrivial-unswitch-divergent-target.ll | 6 +++--- .../SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll | 2 +- llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll | 4 ++-- .../Transforms/SimplifyCFG/switch-transformations-no-lut.ll | 2 +- .../SpeculativeExecution/single-lane-execution.ll | 2 +- .../AMDGPU/reassociate-geps-and-slsr-addrspace.ll | 2 +- .../Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll | 2 +- .../StructurizeCFG/AMDGPU/loop-subregion-misordered.ll | 2 +- .../Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll | 6 +++--- .../Transforms/StructurizeCFG/structurizer-keep-perf-md.ll | 2 +- .../VectorCombine/AMDGPU/as-transition-inseltpoison.ll | 5 +---- llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll | 5 +---- .../AMDGPU/extract-insert-chain-to-shuffles.ll | 2 +- .../VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll | 2 +- .../VectorCombine/AMDGPU/no-scalarize-vector-extract.ll | 4 ++-- 36 files changed, 62 insertions(+), 68 deletions(-) diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll index a8d1c94d59be3..4dad024040698 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { ; GFX7-LABEL: @uadd_sat_v2i16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll index b09022e8289a1..71ff49586dc4d 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { ; GFX7-LABEL: @uadd_sat_v2i16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll index 60c70d74440ef..6a64fc8659de8 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer -slp-threshold=-18 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer -slp-threshold=-18 < %s | FileCheck %s ; Make sure there's no SCEV assert when the indexes are for different ; sized address spaces diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll index 61a50019dac9b..a4ef7a870137b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s define <2 x i16> @bswap_v2i16(<2 x i16> %arg) { ; GFX7-LABEL: @bswap_v2i16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll index 2701e96fcbe9f..27ce78979c32b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s define <2 x i16> @bswap_v2i16(<2 x i16> %arg) { ; GFX7-LABEL: @bswap_v2i16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll index e2d25bae95e98..fdea40954c1fc 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck %s define <2 x i16> @uadd_sat_v9i16_combine_vi16(<9 x i16> %arg0, <9 x i16> %arg1) { ; CHECK-LABEL: @uadd_sat_v9i16_combine_vi16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll index c6dc69e69dd31..3ddc0d66f370b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,dce -S -slp-threshold=-100 -slp-vectorize-hor-store | FileCheck %s --check-prefix=GFX9 +; RUN: opt < %s -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer,dce -S -slp-threshold=-100 -slp-vectorize-hor-store | FileCheck %s --check-prefix=GFX9 @arr = local_unnamed_addr global [32 x i32] zeroinitializer, align 16 @arr64 = local_unnamed_addr global [32 x i64] zeroinitializer, align 16 diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll index 87537c05573ae..3781a57d4ff83 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/invariant-load-no-alias-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -passes="function(slp-vectorizer)" -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 %s -S | FileCheck %s +; RUN: opt -passes="function(slp-vectorizer)" -mtriple=amdgpu12.00-amd-amdhsa %s -S | FileCheck %s define void @test(ptr addrspace(1) %base, ptr addrspace(1) %otherA, ptr addrspace(1) %otherB) #0 { ; CHECK-LABEL: define void @test( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll index 57ca3db075689..f9e1c764a52ed 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX9 %s define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { ; GFX7-LABEL: @uadd_sat_v2i16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll index 429640ea7ff16..388e317278ee5 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s ; FIXME: Should still like to vectorize the memory operations for VI diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll index a3a4ab948519f..2c8a427f780fa 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -passes=slp-vectorizer -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck %s +; RUN: opt -passes=slp-vectorizer -S -mtriple=amdgpu9.06-amd-amdhsa < %s | FileCheck %s define <4 x half> @phis(i1 %cmp1, <4 x half> %in1, <4 x half> %in2) { ; CHECK-LABEL: @phis( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll index 28a77fcb5aff6..4929073d931db 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer,dce < %s | FileCheck -check-prefixes=GCN,VI %s define half @reduction_half4(<4 x half> %a) { ; GFX9-LABEL: @reduction_half4( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll index 1ae6a223406c3..83b4528b4be21 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s define <2 x half> @round_v2f16(<2 x half> %arg) { ; GFX7-LABEL: @round_v2f16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll index fbb23728403b1..1def480fc5bba 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu7.01-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgpu8.03-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes=slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s define <2 x half> @round_v2f16(<2 x half> %arg) { ; GFX7-LABEL: @round_v2f16( diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll index 22b6fb4f0edca..c1e9606aa6342 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX908 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX90A %s +; RUN: opt -S -mtriple=amdgpu9.08-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX908 %s +; RUN: opt -S -mtriple=amdgpu9.0a-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX90A %s ; GCN-LABEL: @fadd_combine ; GFX908: fadd float diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll index 05735168e01dd..7a8a255939f5f 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f64.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1250 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1251 %s +; RUN: opt -S -mtriple=amdgpu12.50-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1250 %s +; RUN: opt -S -mtriple=amdgpu12.51-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1251 %s ; GCN-LABEL: @fadd_combine ; GFX1250: fadd double diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll index f219f2d3037e9..f18a997e93cb3 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2i64.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1250 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1251 %s +; RUN: opt -S -mtriple=amdgpu12.50-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1250 %s +; RUN: opt -S -mtriple=amdgpu12.51-amd-amdhsa -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX1251 %s ; GCN-LABEL: @add_combine ; GFX1250: add i64 diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll index e5c10283f5225..42869ba164e0d 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S --passes=slp-vectorizer -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s +; RUN: opt -S --passes=slp-vectorizer -mtriple=amdgpu-amd-amdhsa < %s | FileCheck %s define void @test() { ; CHECK-LABEL: define void @test() { diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll index a80823c138c17..87a110348f8ec 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \ +; RUN: opt < %s -mtriple=amdgpu-amd-amdhsa -passes=separate-const-offset-from-gep \ ; RUN: -reassociate-geps-verify-no-dead-code -S | FileCheck %s %struct.Packed = type <{ [3 x i32], [8 x i64] }> ; <> means packed diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll index e8d09c518e6b9..bfd638773fb3f 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; Test XOR disjoint bits decomposition into GEP constant offsets. -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \ +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=separate-const-offset-from-gep \ ; RUN: -S < %s | FileCheck %s ; Test GVN eliminates the redundant xor instructions from decomposition. -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \ +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \ ; RUN: -S < %s | FileCheck --check-prefix=GVN %s ; Check that disjoint constants are properly extracted and folded into GEP diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll index 14636f18264e4..2090c805aa7a4 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/crash-in-unreachable-code.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=separate-const-offset-from-gep %s @gv = external local_unnamed_addr addrspace(3) global [16 x i8], align 16 diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/nontrivial-unswitch-divergent-target.ll b/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/nontrivial-unswitch-divergent-target.ll index 4e0b4b64c9da2..4c6f0bb206a7a 100644 --- a/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/nontrivial-unswitch-divergent-target.ll +++ b/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/nontrivial-unswitch-divergent-target.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-- -passes='loop(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-- -passes='loop-mssa(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-- -passes='simple-loop-unswitch<nontrivial>' -verify-memoryssa -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -passes='loop(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -passes='loop-mssa(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -passes='simple-loop-unswitch<nontrivial>' -verify-memoryssa -S < %s | FileCheck %s declare i32 @a() declare i32 @b() diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll b/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll index b1d86a67aa1bd..dcd1938906dab 100644 --- a/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll +++ b/llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -mtriple=amdgcn-- -passes='default<O3>' -S %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -passes='default<O3>' -S %s | FileCheck %s ; Check that loop unswitch happened and condition hoisted out of the loop. ; Condition is uniform so even targets with divergence should perform unswitching. diff --git a/llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll b/llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll index 5a7f189272902..48a97473a0988 100644 --- a/llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll +++ b/llvm/test/Transforms/SimplifyCFG/AMDGPU/cttz-ctlz.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s -; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s +; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=amdgpu6.00-unknown-unknown < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s +; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=amdgpu8.02-unknown-unknown < %s | FileCheck -check-prefix=SI -check-prefix=ALL %s define i64 @test1(i64 %A) { diff --git a/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll b/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll index 929d135ba6220..9ca956fed3760 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -passes='simplifycfg<switch-to-arithmetic>' < %s | FileCheck %s --check-prefix=OPTNOLUT -; RUN: %if amdgpu-registered-target %{ opt -mtriple=amdgcn--amdpal -S -passes='simplifycfg<switch-to-lookup>' < %s | FileCheck %s --check-prefix=TTINOLUT %} +; RUN: %if amdgpu-registered-target %{ opt -mtriple=amdgpu--amdpal -S -passes='simplifycfg<switch-to-lookup>' < %s | FileCheck %s --check-prefix=TTINOLUT %} ; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/SpeculativeExecution/single-lane-execution.ll b/llvm/test/Transforms/SpeculativeExecution/single-lane-execution.ll index ca517d4b91a46..08f3473528b9e 100644 --- a/llvm/test/Transforms/SpeculativeExecution/single-lane-execution.ll +++ b/llvm/test/Transforms/SpeculativeExecution/single-lane-execution.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: amdgpu-registered-target -; RUN: opt -S -passes=speculative-execution -mtriple=amdgcn-- \ +; RUN: opt -S -passes=speculative-execution -mtriple=amdgpu-- \ ; RUN: -spec-exec-only-if-divergent-target \ ; RUN: -spec-exec-max-speculation-cost 4 -spec-exec-max-not-hoisted 3 \ ; RUN: %s | FileCheck %s diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll index 64b562182d20e..e6da4abbaf20d 100644 --- a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll +++ b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -S -mtriple=amdgcn-- -passes=separate-const-offset-from-gep,slsr,gvn < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-- -passes=separate-const-offset-from-gep,slsr,gvn < %s | FileCheck %s diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll index 011624ba9c045..43a37a805f5df 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll @@ -1,6 +1,6 @@ ; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -S -structurizecfg %s | FileCheck %s ; StructurizeCFG::orderNodes used an arbitrary and nonsensical sorting ; function which broke the basic backedge identification algorithm. It diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll index 7c2d8b69bfbb3..e70e7c29cd5d5 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -S -structurizecfg %s | FileCheck %s ; ; StructurizeCFG::orderNodes basically uses a reverse post-order (RPO) traversal of the region ; list to get the order. The only problem with it is that sometimes backedges diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll index 7a2ba286eac1b..bb8ae1ad93b83 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-- -S -o - -structurizecfg -structurizecfg-skip-uniform-regions -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-- -S -o - -passes='structurizecfg<skip-uniform-regions>' -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-- -S -o - -passes=structurizecfg -structurizecfg-skip-uniform-regions -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -S -o - -structurizecfg -structurizecfg-skip-uniform-regions -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -S -o - -passes='structurizecfg<skip-uniform-regions>' -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -S -o - -passes=structurizecfg -structurizecfg-skip-uniform-regions -structurizecfg-relaxed-uniform-regions < %s | FileCheck %s define amdgpu_cs void @uniform(i32 inreg %v) { ; CHECK-LABEL: @uniform( diff --git a/llvm/test/Transforms/StructurizeCFG/structurizer-keep-perf-md.ll b/llvm/test/Transforms/StructurizeCFG/structurizer-keep-perf-md.ll index 583c97852ff6d..b0968a36f6bd5 100644 --- a/llvm/test/Transforms/StructurizeCFG/structurizer-keep-perf-md.ll +++ b/llvm/test/Transforms/StructurizeCFG/structurizer-keep-perf-md.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-- -passes=structurizecfg %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu-- -passes=structurizecfg %s | FileCheck -check-prefix=OPT %s define amdgpu_ps i32 @if_else(i32 %0) { ; OPT-LABEL: define amdgpu_ps i32 @if_else( diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll index c021c2e244cf8..f51d17480222f 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll @@ -1,8 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s - -; ModuleID = 'load-as-transition.ll' -target triple = "amdgcn-amd-amdhsa" +; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgpu-amd-amdhsa | FileCheck %s %struct.hoge = type { float } diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll index 005ed3114dc74..59e29ad754b74 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll @@ -1,8 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s - -; ModuleID = 'load-as-transition.ll' -target triple = "amdgcn-amd-amdhsa" +; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgpu-amd-amdhsa | FileCheck %s %struct.hoge = type { float } diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll index b6ba6eb984c85..6422347864a78 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-chain-to-shuffles.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-- -mcpu=gfx1100 -passes=vector-combine < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu11.00-- -passes=vector-combine < %s | FileCheck -check-prefix=OPT %s ; Generated from amdgpu-promote-alloca on array of vectors ; VectorCombiner should recognize chain of extract-insert vectors diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll index 19cd301a32ebe..e0981ef6281f8 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/narrow-phi-of-shuffles.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=vector-combine -S %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=vector-combine -S %s | FileCheck %s define <2 x i8> @shuffle_v2i8(<2 x i8> %arg0, i1 %cond) { ; CHECK-LABEL: define <2 x i8> @shuffle_v2i8( diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/no-scalarize-vector-extract.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/no-scalarize-vector-extract.ll index 45e3e2db4e429..7c7847147e022 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/no-scalarize-vector-extract.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/no-scalarize-vector-extract.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes=vector-combine < %s | FileCheck -check-prefix=GFX9 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=vector-combine < %s | FileCheck -check-prefix=GFX12 %s +; RUN: opt -S -mtriple=amdgpu9.42-amd-amdhsa -passes=vector-combine < %s | FileCheck -check-prefix=GFX9 %s +; RUN: opt -S -mtriple=amdgpu12.50-amd-amdhsa -passes=vector-combine < %s | FileCheck -check-prefix=GFX12 %s ; Test that VectorCombine does not scalarize v16i8/v8i8/v4i8 loads from LDS. ; Vector loads can be efficiently lowered to ds_read_b128/b64/b32 instructions, _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
