https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/208811
Continue migrating command-line target spelling on RUN lines to the folded amdgpu subarch triple form, covering more Transforms tests. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From cf1f915bf39927b3f54e21d1f7ed95adc4e175e2 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 09:52:16 +0200 Subject: [PATCH] AMDGPU: Migrate Analysis/Transforms tests to amdgpu subarch triple (3) Continue migrating command-line target spelling on RUN lines to the folded amdgpu subarch triple form, covering more Transforms tests. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../Transforms/InstCombine/AMDGPU/fmul_legacy.ll | 2 +- llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll | 10 +++++----- .../test/Transforms/InstCombine/AMDGPU/issue68120.ll | 2 +- .../AMDGPU/lane-index-simplify-demanded-bits.ll | 6 +++--- .../AMDGPU/llvm.amdgcn.implicitarg.ptr.ll | 4 ++-- .../InstCombine/AMDGPU/mbcnt-negative-cases.ll | 2 +- .../InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll | 2 +- .../InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll | 2 +- .../InstCombine/AMDGPU/memcpy-from-constant.ll | 2 +- .../test/Transforms/InstCombine/AMDGPU/mfma-scale.ll | 2 +- .../test/Transforms/InstCombine/AMDGPU/permlane64.ll | 2 +- .../InstCombine/AMDGPU/ptr-replace-alloca.ll | 2 +- .../InstCombine/AMDGPU/sendmsg-m0-poison.ll | 8 ++++---- .../AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll | 2 +- llvm/test/Transforms/InstCombine/AMDGPU/tan.ll | 2 +- .../AMDGPU/wave-shuffle-patterns-wave64.ll | 4 ++-- .../InstCombine/AMDGPU/wave-shuffle-patterns.ll | 6 +++--- .../Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll | 2 +- llvm/test/Transforms/InstCombine/exp2-1.ll | 2 +- llvm/test/Transforms/InstCombine/pow-1.ll | 2 +- .../JumpThreading/divergent-target-test.ll | 2 +- llvm/test/Transforms/LICM/AMDGPU/bitcast.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/aa-metadata.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/addrspace-7.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/complex-index.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/extended-index.ll | 4 ++-- .../AMDGPU/fence-noalias-metadata.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/gep-bitcast.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/insertion-point.ll | 4 ++-- .../AMDGPU/interleaved-mayalias-store.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/invariant-load.ll | 4 ++-- .../AMDGPU/merge-stores-private.ll | 12 ++++++------ .../LoadStoreVectorizer/AMDGPU/merge-stores.ll | 2 +- .../AMDGPU/merge-vectors-complex.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/merge-vectors.ll | 4 ++-- .../LoadStoreVectorizer/AMDGPU/missing-alignment.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/multiple_tails.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/no-implicit-float.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/opaque_ptr.ll | 2 +- .../Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/pointer-elements.ll | 2 +- .../AMDGPU/selects-inseltpoison.ll | 2 +- .../Transforms/LoadStoreVectorizer/AMDGPU/selects.ll | 2 +- .../AMDGPU/store_with_aliasing_load.ll | 2 +- .../LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll | 4 ++-- .../AMDGPU/vectorize-redund-loads.ll | 2 +- .../AMDGPU/weird-type-accesses.ll | 2 +- llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll | 2 +- .../Transforms/LoopStrengthReduce/AMDGPU/atomics.ll | 2 +- .../AMDGPU/lsr-invalid-ptr-extend.ll | 2 +- .../AMDGPU/lsr-postinc-pos-addrspace.ll | 2 +- .../AMDGPU/preserve-addrspace-assert.ll | 2 +- .../Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll | 2 +- .../LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll | 2 +- .../Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll | 2 +- .../AMDGPU/unroll-convergent-uniform-tripcount.ll | 2 +- .../LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll | 2 +- .../Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll | 2 +- .../LoopUnroll/AMDGPU/unroll-for-private.ll | 2 +- .../Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll | 2 +- .../LoopVectorize/AMDGPU/divergent-runtime-check.ll | 4 ++-- .../Transforms/LoopVectorize/AMDGPU/packed-fp32.ll | 2 +- .../Transforms/LoopVectorize/AMDGPU/packed-fp64.ll | 2 +- .../Transforms/LoopVectorize/AMDGPU/packed-math.ll | 6 +++--- .../AMDGPU/unroll-in-loop-vectorizer.ll | 2 +- llvm/test/Transforms/MemCpyOpt/no-libcalls.ll | 4 ++-- llvm/test/Transforms/OpenMP/custom_state_machines.ll | 4 ++-- .../OpenMP/custom_state_machines_pre_lto.ll | 6 +++--- .../OpenMP/heap-to-shared-missing-declarations.ll | 2 +- llvm/test/Transforms/OpenMP/spmdization.ll | 6 +++--- llvm/test/Transforms/OpenMP/spmdization_indirect.ll | 2 +- .../Transforms/OpenMP/spmdization_kernel_env_dep.ll | 2 +- .../PhaseOrdering/AMDGPU/infer-address-space.ll | 12 ++++++------ llvm/test/Transforms/PhaseOrdering/varargs.ll | 2 +- .../AMDGPU/expand-mem-intrinsics.ll | 2 +- .../AMDGPU/memset-pattern.ll | 4 ++-- .../AMDGPU/expamd-masked-load.ll | 2 +- .../AMDGPU/expand-masked-gather.ll | 2 +- .../AMDGPU/expand-masked-scatter.ll | 2 +- .../AMDGPU/expand-masked-store.ll | 2 +- .../AMDGPU/preserve-inbounds.ll | 2 +- .../split-gep-and-gvn-addrspace-addressing-modes.ll | 2 +- 82 files changed, 125 insertions(+), 125 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll b/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll index 4600831b60b87..440c28a0d51c4 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -passes=instcombine -S | FileCheck %s +; RUN: opt < %s -mtriple=amdgpu-amd-amdhsa -passes=instcombine -S | FileCheck %s ; Simplify to +0.0. define float @test_zero(float %x) { diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll index ee5ccf5af987d..805f552c95d74 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx700 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX7 %s -; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx810 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s -; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s -; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s -; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1100 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s +; RUN: opt -mtriple=amdgpu7.00--amdpal -S -passes=instcombine %s | FileCheck --check-prefixes=GFX7 %s +; RUN: opt -mtriple=amdgpu8.10--amdpal -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s +; RUN: opt -mtriple=amdgpu9.00--amdpal -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s +; RUN: opt -mtriple=amdgpu10.10--amdpal -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s +; RUN: opt -mtriple=amdgpu11.00--amdpal -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) { ; GFX7-LABEL: @image_sample_2d_fptrunc_to_d16( diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll b/llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll index 346c64f096ba3..abb66aa6e89f7 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/issue68120.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=instcombine %s | FileCheck %s ; It is illegal to pass ptr addrspace(4) in %arg by addrspacecasting ; to ptr addrspace(5) to pass off to the stack argument. A temporary diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll b/llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll index 327d68bdf550e..bcf03bd0f6395 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize32 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -mattr=+wavefrontsize32 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s ; -------------------------------------------------------------------- ; llvm.amdgcn.readlane diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll index 048222d0bb22b..3f76e848979e7 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -passes='instcombine' -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s --check-prefix=AMDHSA -; RUN: opt -S -passes='instcombine' -mtriple=amdgcn-mesa-mesa3d < %s | FileCheck %s --check-prefix=MESA +; RUN: opt -S -passes='instcombine' -mtriple=amdgpu-amd-amdhsa < %s | FileCheck %s --check-prefix=AMDHSA +; RUN: opt -S -passes='instcombine' -mtriple=amdgpu-mesa-mesa3d < %s | FileCheck %s --check-prefix=MESA ; InstCombine added retattr dereferenceable(bytes) to a "call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()". diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll index 6e3f012ea2c66..f1d1375cf26cf 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-codegenprepare < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-codegenprepare < %s | FileCheck %s ; Test negative cases where mbcnt optimizations should NOT be applied diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll index fdb8ca7e5c8eb..55a8f74ff893f 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave32-optimizations.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=amdgpu-codegenprepare < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu10.30-amd-amdhsa -passes=amdgpu-codegenprepare < %s | FileCheck %s ; Test mbcnt optimizations for wave32 architecture ; Covers: simple replacement, bitmask optimization, copy optimization diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll index 7d2255c3ab488..e02849699e557 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-wave64-optimizations.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=amdgpu-codegenprepare < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu9.06-amd-amdhsa -passes=amdgpu-codegenprepare < %s | FileCheck %s ; Test full mbcnt pattern optimization for wave64 architecture ; Covers: full pattern optimization diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll b/llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll index 74992d341a0f0..85868da11db35 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -amdgpu-aa-wrapper -amdgpu-aa -instcombine -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -S -amdgpu-aa-wrapper -amdgpu-aa -instcombine -o - %s | FileCheck %s ; Make sure the optimization from memcpy-from-global.ll happens, but ; the constant source is not a global variable. diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll b/llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll index 709f143a4745a..e517d92ee8270 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=instcombine < %s | FileCheck %s ; -------------------------------------------------------------------- ; Incorrect signature for format cases (IR vector too large) 16x16x128 diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll b/llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll index c480ecf6a8b31..84cb66ef74436 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -passes=instcombine -S | FileCheck %s +; RUN: opt < %s -mtriple=amdgpu-amd-amdhsa -passes=instcombine -S | FileCheck %s ; Optimize the intrinsic away if the argument is uniform. define i32 @test_constant() { diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll b/llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll index 90877be255e0f..3826542c87a8f 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=instcombine -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=instcombine -S < %s | FileCheck %s %struct.type = type { [256 x <2 x i64>] } @g1 = external hidden addrspace(3) global %struct.type, align 16 diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll b/llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll index 3787452db1943..bcf87283b38f4 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/sendmsg-m0-poison.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,DEFAULT -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX9 -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX10 -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX11 +; RUN: opt < %s -mtriple=amdgpu -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,DEFAULT +; RUN: opt < %s -mtriple=amdgpu9.00-amd-amdhsa -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX9 +; RUN: opt < %s -mtriple=amdgpu10.10-amd-amdhsa -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX10 +; RUN: opt < %s -mtriple=amdgpu11.00-amd-amdhsa -passes=instcombine -S | FileCheck %s --check-prefixes=CHECK,GFX11 ; Test that the m0 operand is folded to poison for message types that don't use it. ; For the default target (no mcpu), conflicting encodings (IDs 2, 3) should NOT be folded. diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll b/llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll index 1082c6ddb898b..6cd8489dfe757 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=instcombine < %s | FileCheck %s @gv = constant i32 0 diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/tan.ll b/llvm/test/Transforms/InstCombine/AMDGPU/tan.ll index 62160a6d3063a..5913ef85478ae 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/tan.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/tan.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn--amdpal -S -passes=instcombine <%s | FileCheck --check-prefixes=GCN %s +; RUN: opt -mtriple=amdgpu--amdpal -S -passes=instcombine <%s | FileCheck --check-prefixes=GCN %s ; Check that sin/cos is not folded to tan on amdgcn. diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll b/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll index a225980ec0fa1..c2f55e729feae 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11-W64 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX9 +; RUN: opt -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11-W64 +; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX9 ; Wave64 shuffle patterns. The index must be the full wave64 thread ID, ; mbcnt.hi(-1, mbcnt.lo(-1, 0)); using mbcnt.lo alone would only yield diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll b/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll index 3b8217e03c6f6..bb122ed694ce2 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11-W64 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX9 +; RUN: opt -mtriple=amdgpu11.00-amd-amdhsa -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11 +; RUN: opt -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX11-W64 +; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=instcombine -S < %s | FileCheck %s --check-prefixes=GFX9 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll b/llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll index 5cff45225958b..1ff15ad9c1976 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/wmma-f8f6f4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=instcombine < %s | FileCheck %s ; ------------------------------------------------------------------------------------ ; Incorrect signature for format cases (IR vector too large) wmma.f32.16x16x128.f8f6f4 diff --git a/llvm/test/Transforms/InstCombine/exp2-1.ll b/llvm/test/Transforms/InstCombine/exp2-1.ll index 6824d1babae7a..f924eaaddde8d 100644 --- a/llvm/test/Transforms/InstCombine/exp2-1.ll +++ b/llvm/test/Transforms/InstCombine/exp2-1.ll @@ -5,7 +5,7 @@ ; RUN: opt < %s -passes=instcombine -S -mtriple=msp430 | FileCheck %s -check-prefixes=LDEXP16 ; RUN: opt < %s -passes=instcombine -S -mtriple=i386-pc-win32 | FileCheck %s -check-prefixes=NOLDEXPF ; RUN: opt < %s -passes=instcombine -S -mtriple=i386-windows-gnu | FileCheck %s -check-prefixes=NOLDEXPF -; RUN: opt < %s -passes=instcombine -S -mtriple=amdgcn-unknown-unknown | FileCheck %s -check-prefixes=NOLDEXP +; RUN: opt < %s -passes=instcombine -S -mtriple=amdgpu-unknown-unknown | FileCheck %s -check-prefixes=NOLDEXP target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/llvm/test/Transforms/InstCombine/pow-1.ll b/llvm/test/Transforms/InstCombine/pow-1.ll index 4fd2d252e8c2a..42f27f7bc19ef 100644 --- a/llvm/test/Transforms/InstCombine/pow-1.ll +++ b/llvm/test/Transforms/InstCombine/pow-1.ll @@ -14,7 +14,7 @@ ; RUN: opt -passes=instcombine -S < %s -mtriple=i386-pc-windows-msvc | FileCheck %s --check-prefixes=CHECK,LIB,CHECK-NO-EXP10,VC19,VC51 ; RUN: opt -passes=instcombine -S < %s -mtriple=x86_64-pc-windows-msvc18 | FileCheck %s --check-prefixes=CHECK,LIB,CHECK-NO-EXP10,VC64 ; RUN: opt -passes=instcombine -S < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s --check-prefixes=CHECK,LIB,CHECK-NO-EXP10,VC19,VC83 -; RUN: opt -passes=instcombine -S < %s -mtriple=amdgcn-- | FileCheck %s --check-prefixes=CHECK,CHECK-NO-EXP10,NOLIB +; RUN: opt -passes=instcombine -S < %s -mtriple=amdgpu-- | FileCheck %s --check-prefixes=CHECK,CHECK-NO-EXP10,NOLIB ; NOTE: The readonly attribute on the pow call should be preserved ; in the cases below where pow is transformed into another function call. diff --git a/llvm/test/Transforms/JumpThreading/divergent-target-test.ll b/llvm/test/Transforms/JumpThreading/divergent-target-test.ll index 2e3fa50a1f7f9..c4dd6939e7b3e 100644 --- a/llvm/test/Transforms/JumpThreading/divergent-target-test.ll +++ b/llvm/test/Transforms/JumpThreading/divergent-target-test.ll @@ -1,5 +1,5 @@ ; REQUIRES: amdgpu-registered-target && x86-registered-target -; RUN: opt < %s -mtriple=amdgcn -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,DIVERGENT +; RUN: opt < %s -mtriple=amdgpu -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,DIVERGENT ; RUN: opt < %s -mtriple=x86_64 -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,UNIFORM ; Here we assure that for the target with no branch divergence usual Jump Threading optimization performed diff --git a/llvm/test/Transforms/LICM/AMDGPU/bitcast.ll b/llvm/test/Transforms/LICM/AMDGPU/bitcast.ll index 6c610130fedc4..3e7c3b09ef998 100644 --- a/llvm/test/Transforms/LICM/AMDGPU/bitcast.ll +++ b/llvm/test/Transforms/LICM/AMDGPU/bitcast.ll @@ -1,4 +1,4 @@ -; RUN: opt -passes=licm -mtriple=amdgcn -S -o - %s | FileCheck %s +; RUN: opt -passes=licm -mtriple=amdgpu -S -o - %s | FileCheck %s ; CHECK-LABEL: foo ; CHECK: ret diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll index eab802a9be813..354537acf1218 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa,scoped-noalias-aa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefix=SCOPE %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefix=NOSCOPE %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa,scoped-noalias-aa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefix=SCOPE %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefix=NOSCOPE %s ; This fails to vectorize if the !alias.scope is not used diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll index 907df9b211a8d..34aba4bd51755 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/addrspace-7.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s define { float, float } @f() { ; CHECK-LABEL: define { float, float } @f() { diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll index b558c0996100e..7b4f58daa1375 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s declare i64 @_Z12get_local_idj(i32) diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll index 009c3b708d0c1..7ce03a535a25a 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s declare i32 @llvm.amdgcn.workitem.id.x() #1 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll index d2f19efcaf160..bc0c027156451 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa,scoped-noalias-aa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa,scoped-noalias-aa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; Test that getModRefInfo(FenceInst, Loc) uses scoped noalias metadata on the ; fence to prove it cannot affect a given memory location. Without this, the diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll index 807ef651dbb32..389187de5226b 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn--amdhsa -passes=load-store-vectorizer < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn--amdhsa -passes='function(load-store-vectorizer)' < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu--amdhsa -passes=load-store-vectorizer < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu--amdhsa -passes='function(load-store-vectorizer)' < %s | FileCheck %s ; Check that vectorizer can find a GEP through bitcast ; CHECK-LABEL: @vect_zext_bitcast_f32_to_i32_idx diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll index 7e8202b9de37c..2375aef9ab06a 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s ; Check position of the inserted vector load/store. Vectorized loads should be ; inserted at the position of the first load in the chain, and stores should be diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll index 20c67702a2c9d..36ceccdf0ef90 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s ; This is NOT OK to vectorize, as either load may alias either store. diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll index 0a09010dadc92..ffba51de99845 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s ; CHECK-LABEL: @interleave ; CHECK: load <2 x double>, ptr addrspace(1) %{{.}}, align 8{{$}} diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll index 3bbc7d6725962..dd0f3bc2f1d8b 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll @@ -1,9 +1,9 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-ALIGNED,ALIGNED,ALL %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ALIGNED,ALL %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ALIGNED,ALL %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-UNALIGNED,UNALIGNED,ALL %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-UNALIGNED,UNALIGNED,ALL %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-UNALIGNED,UNALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-4,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-ALIGNED,ALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-8,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-16,-unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-4,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-UNALIGNED,UNALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-8,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-UNALIGNED,UNALIGNED,ALL %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -mattr=+max-private-element-size-16,+unaligned-scratch-access -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-UNALIGNED,UNALIGNED,ALL %s ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32 ; ELT4-ALIGNED: store i32 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll index 6c9f888d69849..f8c4a92c0cfc3 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa --mcpu=hawaii -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu7.01-amd-amdhsa --passes=load-store-vectorizer -S -o - %s | FileCheck %s ; Copy of test/CodeGen/AMDGPU/merge-stores.ll with some additions ; TODO: Vector element tests diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll index 5c331a9c9fe39..928baab8b38e1 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s define void @merge_i32_v2i16_f32_v4i8(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) { ; CHECK-LABEL: define void @merge_i32_v2i16_f32_v4i8( diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll index a696a5421f606..1b1ac16c93c83 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s \ +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s \ ; RUN: | FileCheck --check-prefixes=CHECK,CHECK-OOB-STRICT %s ; RUN: cp %s %t.relaxed.ll && chmod +w %t.relaxed.ll ; RUN: printf '\n!llvm.module.flags = !{!0}\n!0 = !{i32 7, !"amdgpu.buffer.oob.mode", i32 1}\n' >> %t.relaxed.ll -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %t.relaxed.ll \ +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %t.relaxed.ll \ ; RUN: | FileCheck --check-prefixes=CHECK,CHECK-OOB-RELAXED %s define amdgpu_kernel void @merge_v2i32_v2i32(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b) #0 { diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll index 688a25055d626..cfe99b3aff162 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu8.02-- -passes=load-store-vectorizer -S -o - %s | FileCheck %s @lds = internal addrspace(3) global [512 x float] undef, align 4 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll index 57da5976b3cfa..b86e1e8d13b2d 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=GCN %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=GCN %s ; Checks that there is no crash when there are multiple tails ; for a the same head starting a chain. diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll index 0b2e1791084dc..72a1d784d7831 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; CHECK-LABEL: @no_implicit_float( ; CHECK: store i32 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll index c62744082f8ec..9516ffd742a2b 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; Vectorize and emit valid code (Issue #54896). diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll index d40d2771af17d..fd8b8c011d0d0 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; CHECK-LABEL: @optnone( ; CHECK: store i32 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll index 2076a9dd962fe..eb336c9b7e21e 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s declare i32 @llvm.amdgcn.workitem.id.x() #1 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll index eecc91648e751..4717fae261f1c 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer,dce -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer,dce -S -o - %s | FileCheck %s define void @base_case(i1 %cnd, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %out) { ; CHECK-LABEL: @base_case diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll index 2471b64b92754..5b09372023360 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer,dce -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer,dce -S -o - %s | FileCheck %s define void @base_case(i1 %cnd, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %out) { ; CHECK-LABEL: @base_case diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll index 69fdf6d0f0130..24fc988c20bd1 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; Check that, in the presence of an aliasing load, the stores preceding the ; aliasing load are safe to vectorize. diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll index 59c30e12868b8..7772a9393d37b 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn--amdpal -passes=load-store-vectorizer -S -o - %s | FileCheck --check-prefix=OOB-STRICT %s +; RUN: opt -mtriple=amdgpu--amdpal -passes=load-store-vectorizer -S -o - %s | FileCheck --check-prefix=OOB-STRICT %s ; RUN: cp %s %t.relaxed.ll && chmod +w %t.relaxed.ll ; RUN: printf '\n!llvm.module.flags = !{!0}\n!0 = !{i32 7, !"amdgpu.buffer.oob.mode", i32 1}\n' >> %t.relaxed.ll -; RUN: opt -mtriple=amdgcn--amdpal -passes=load-store-vectorizer -S -o - %t.relaxed.ll \ +; RUN: opt -mtriple=amdgpu--amdpal -passes=load-store-vectorizer -S -o - %t.relaxed.ll \ ; RUN: | FileCheck --check-prefixes=OOB-RELAXED %s ; The test checks that the "amdgpu.buffer.oob.mode" module flag diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll index 802795da47894..bb0e6067bf248 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s define void @onevec(ptr %ptr) { ; CHECK-LABEL: define void @onevec( diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll index 842268a8b853b..f325c755e2260 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s ; Checks that we don't merge loads/stores of types smaller than one ; byte, or vectors with elements smaller than one byte. diff --git a/llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll b/llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll index 5f49d6c05ae4e..706b3e4a59d45 100644 --- a/llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll +++ b/llvm/test/Transforms/LoopIdiom/AMDGPU/popcnt.ll @@ -1,4 +1,4 @@ -; RUN: opt -passes=loop-idiom -mtriple=amdgcn-- -S < %s | FileCheck %s +; RUN: opt -passes=loop-idiom -mtriple=amdgpu-- -S < %s | FileCheck %s ; Mostly copied from x86 version. diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll index 33afe40efb380..4743cabb81364 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-- -mcpu=bonaire -loop-reduce < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu7.04-- -loop-reduce < %s | FileCheck -check-prefix=OPT %s ; Make sure the pointer / address space of AtomicRMW is considered diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll index fa7c094499e03..dd45612825bf4 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn -loop-reduce -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu -loop-reduce -S < %s | FileCheck %s ; REQUIRES: asserts ; Test that LSR does not attempt to extend a pointer type to an integer type, diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll index 810f5f27be076..32ed5477c086b 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn -mcpu=bonaire -loop-reduce -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu7.04 -loop-reduce -S < %s | FileCheck %s ; Test various conditions where OptimizeLoopTermCond doesn't look at a ; memory instruction use and fails to find the address space. diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll index 2bd4d42b8ac02..5f4357c0fe85c 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -loop-reduce %s | FileCheck %s ; Test for assert resulting from inconsistent isLegalAddressingMode ; answers when the address space was dropped from the query. diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll index 769f78f422573..e91fa16137451 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-- -passes=loop-unroll -S %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -passes=loop-unroll -S %s | FileCheck %s ; Verify that AMDGPU enables runtime loop unrolling for loops whose trip ; count is not known at compile time. diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll index 0bb8df260afca..5c44643ea6e46 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-analyze-small-loops.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=loop-unroll < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-unknown-amdhsa -passes=loop-unroll < %s | FileCheck %s ; Test that max iterations count to analyze (specific for the target) ; is enough to make the inner loop completely unrolled diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll index 1413ec225c332..e1ca9d86c980f 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu7.01-unknown-amdhsa -passes=loop-unroll -S < %s | FileCheck %s ; CHECK-LABEL: @test_unroll_convergent_barrier( ; CHECK: call void @llvm.amdgcn.s.barrier() diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll index acd6d285c463c..d904fba1402d4 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-convergent-uniform-tripcount.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --version 6 -; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -unroll-runtime -unroll-allow-partial -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu7.01-unknown-amdhsa -passes=loop-unroll -unroll-runtime -unroll-allow-partial -S < %s | FileCheck %s declare void @llvm.amdgcn.s.barrier() #0 diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll index d189f91704852..004be1ec6084e 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -unroll-threshold=57 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.01-unknown-amdhsa -passes=loop-unroll -unroll-threshold=57 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s @indices = external global [16 x i32] diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll index 6e0798620f0bd..aeed9bec1d9ed 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-call.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii -passes=loop-unroll -unroll-threshold=100 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu7.01-unknown-amdhsa -passes=loop-unroll -unroll-threshold=100 -unroll-peel-count=0 -unroll-allow-partial=false -unroll-max-iteration-count-to-analyze=16 < %s | FileCheck %s ; CHECK-LABEL: @test_intrinsic_call_cost( ; CHECK-NOT: br i1 diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll index 575d2ffe16c9a..c577ae890ec3a 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-unknown-amdhsa -passes=loop-unroll -S %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-unknown-amdhsa -passes=loop-unroll -S %s | FileCheck %s ; Check that we full unroll loop to be able to eliminate alloca ; CHECK-LABEL: @non_invariant_ind diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll index ffc0ae9ae52bb..af437ba1d8a6a 100644 --- a/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll +++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-threshold.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -S -mtriple=amdgcn-- -passes=loop-unroll | FileCheck %s +; RUN: opt < %s -S -mtriple=amdgpu-- -passes=loop-unroll | FileCheck %s ; Check the handling of amdgpu.loop.unroll.threshold metadata which can be used to ; set the default threshold for a loop. This metadata overrides both the AMDGPU diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll index 5e957205b546e..c134075d4d3f8 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -passes=loop-vectorize < %s | FileCheck -check-prefixes=GCN %s -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -passes=loop-vectorize -pass-remarks-analysis='loop-vectorize' < %s 2>&1 | FileCheck -check-prefixes=REMARK %s +; RUN: opt -S -mtriple=amdgpu9.00-unknown-amdhsa -passes=loop-vectorize < %s | FileCheck -check-prefixes=GCN %s +; RUN: opt -S -mtriple=amdgpu9.00-unknown-amdhsa -passes=loop-vectorize -pass-remarks-analysis='loop-vectorize' < %s 2>&1 | FileCheck -check-prefixes=REMARK %s ; GCN-LABEL: @runtime_check_divergent_target( ; GCN-NOT: load <2 x half> diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll index e43a14bb47603..6faa95d7bc864 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp32.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX90A %s +; RUN: opt -mtriple=amdgpu9.0a-amd-amdhsa < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX90A %s ; GFX90A-LABEL: @vectorize_v2f32_loop( ; GFX90A-COUNT-2: load <2 x float> diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll index 7fb0480fde996..5339bd034d83d 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-fp64.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX1251 %s +; RUN: opt -mtriple=amdgpu12.51-amd-amdhsa < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX1251 %s ; GFX1251-LABEL: @vectorize_v2f64_loop( ; GFX1251-COUNT-2: load <2 x double> diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll index c803fc4cf308b..ee2f9981c1361 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX9 %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s -passes=loop-vectorize -S | FileCheck -check-prefix=VI %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s -passes=loop-vectorize -S | FileCheck -check-prefix=CI %s +; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa < %s -passes=loop-vectorize -S | FileCheck -check-prefix=GFX9 %s +; RUN: opt -mtriple=amdgpu8.03-amd-amdhsa < %s -passes=loop-vectorize -S | FileCheck -check-prefix=VI %s +; RUN: opt -mtriple=amdgpu7.01-amd-amdhsa < %s -passes=loop-vectorize -S | FileCheck -check-prefix=CI %s define half @vectorize_v2f16_loop(ptr addrspace(1) noalias %s) { ; GFX9-LABEL: @vectorize_v2f16_loop( diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll index 0ef6620e74a65..f6e00807b7114 100644 --- a/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji -passes=loop-vectorize < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu8.03-unknown-amdhsa -passes=loop-vectorize < %s | FileCheck %s ; For AMDGPU, loop unroll in loop vectorizer is disabled when VF==1. diff --git a/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll b/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll index 7ba28cfa922b6..f6b6fcd2d0ac7 100644 --- a/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll +++ b/llvm/test/Transforms/MemCpyOpt/no-libcalls.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -passes=memcpyopt -mtriple=x86_64 < %s | FileCheck %s --check-prefixes=CHECK,LIBCALLS -; RUN: opt -S -passes=memcpyopt -mtriple=amdgcn-- < %s | FileCheck %s --check-prefixes=CHECK,NO-LIBCALLS -; RUN: opt -S -passes=memcpyopt -mtriple=amdgcn-- -enable-memcpyopt-without-libcalls < %s \ +; RUN: opt -S -passes=memcpyopt -mtriple=amdgpu-- < %s | FileCheck %s --check-prefixes=CHECK,NO-LIBCALLS +; RUN: opt -S -passes=memcpyopt -mtriple=amdgpu-- -enable-memcpyopt-without-libcalls < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,LIBCALLS ; REQUIRES: amdgpu-registered-target diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines.ll b/llvm/test/Transforms/OpenMP/custom_state_machines.ll index 8f025a8a06cb3..a03a4b7f3fa67 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs -; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU +; RUN: opt --mtriple=amdgpu-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX -; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU-DISABLED +; RUN: opt --mtriple=amdgpu-amd-amdhsa --data-layout=A5 -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU-DISABLED ; RUN: opt --mtriple=nvptx64-- -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX-DISABLED ;; void p0(void); diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll b/llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll index 6df38d17a0785..46de49d4fb7e3 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines_pre_lto.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs -; RUN: opt --mtriple=amdgcn-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU1 +; RUN: opt --mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU1 ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=NVPTX1 -; RUN: opt --mtriple=amdgcn-amd-amdhsa -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU2 -; RUN: opt --mtriple=amdgcn-amd-amdhsa -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=AMDGPU3 +; RUN: opt --mtriple=amdgpu-amd-amdhsa -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU2 +; RUN: opt --mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=AMDGPU3 ; RUN: opt --mtriple=nvptx64-- -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=NVPTX2 ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=NVPTX3 diff --git a/llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll b/llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll index d81f34f3c4273..b93e2d7b2ca85 100644 --- a/llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll +++ b/llvm/test/Transforms/OpenMP/heap-to-shared-missing-declarations.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals ; REQUIRES: amdgpu-registered-target -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s define internal void @outlined0() { ; CHECK: Function Attrs: nounwind diff --git a/llvm/test/Transforms/OpenMP/spmdization.ll b/llvm/test/Transforms/OpenMP/spmdization.ll index d5c66f3933a1e..8a613d322721f 100644 --- a/llvm/test/Transforms/OpenMP/spmdization.ll +++ b/llvm/test/Transforms/OpenMP/spmdization.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 6 -; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU +; RUN: opt --mtriple=amdgpu-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX -; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt -openmp-opt-disable-spmdization < %s | FileCheck %s --check-prefix=AMDGPU-DISABLED1 -; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=AMDGPU-DISABLED2 +; RUN: opt --mtriple=amdgpu-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt -openmp-opt-disable-spmdization < %s | FileCheck %s --check-prefix=AMDGPU-DISABLED1 +; RUN: opt --mtriple=amdgpu-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=AMDGPU-DISABLED2 ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt -openmp-opt-disable-spmdization < %s | FileCheck %s --check-prefix=NVPTX-DISABLED1 ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=NVPTX-DISABLED2 diff --git a/llvm/test/Transforms/OpenMP/spmdization_indirect.ll b/llvm/test/Transforms/OpenMP/spmdization_indirect.ll index b65bbdf9d51ee..1de719e1b85a8 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_indirect.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_indirect.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 6 -; RUN: opt --mtriple=amdgcn-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU +; RUN: opt --mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU ; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX %struct.ident_t = type { i32, i32, i32, i32, ptr } diff --git a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll index 67dbbeb62d1cc..de994a02bf747 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals -; RUN: opt --mtriple=amdgcn-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU +; RUN: opt --mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU target triple = "amdgcn-amd-amdhsa" diff --git a/llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll b/llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll index 38ad7ed28dee4..168083f285b03 100644 --- a/llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll +++ b/llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S -O1 -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s -; RUN: opt -S -O2 -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s -; RUN: opt -S -O3 -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s -; RUN: opt -S -passes='lto<O1>' -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=NO-INFER %s -; RUN: opt -S -passes='lto<O2>' -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s -; RUN: opt -S -passes='lto<O3>' -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s +; RUN: opt -S -O1 -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s +; RUN: opt -S -O2 -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s +; RUN: opt -S -O3 -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s +; RUN: opt -S -passes='lto<O1>' -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=NO-INFER %s +; RUN: opt -S -passes='lto<O2>' -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s +; RUN: opt -S -passes='lto<O3>' -mtriple=amdgpu-amd-amdhsa %s -o - | FileCheck --check-prefix=INFER %s %struct.data = type { ptr, i32 } diff --git a/llvm/test/Transforms/PhaseOrdering/varargs.ll b/llvm/test/Transforms/PhaseOrdering/varargs.ll index 70c63a800e111..2a5ee4746e484 100644 --- a/llvm/test/Transforms/PhaseOrdering/varargs.ll +++ b/llvm/test/Transforms/PhaseOrdering/varargs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -mtriple=amdgcn-- -S -passes='lto<O2>' < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-- -S -passes='lto<O2>' < %s | FileCheck %s target triple = "amdgcn-amd-amdhsa" ; REQUIRES: amdgpu-registered-target diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll index 3d2a86f50027b..ed497d4ddb530 100644 --- a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -mtriple=amdgcn-amd-amdhsa -p=debugify,pre-isel-intrinsic-lowering,check-debugify -S < %s | FileCheck %s +; RUN: opt -mtriple=amdgpu-amd-amdhsa -p=debugify,pre-isel-intrinsic-lowering,check-debugify -S < %s | FileCheck %s define protected amdgpu_kernel void @memcpy(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 noundef %n) { ; CHECK-LABEL: define protected amdgpu_kernel void @memcpy( diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll index e79e330190722..829f29ecc6265 100644 --- a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -p=pre-isel-intrinsic-lowering -S < %s | FileCheck -check-prefixes=CHECK,DEFAULT %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -p=pre-isel-intrinsic-lowering -S -amdgpu-memcpy-loop-unroll=2 %s -o - | FileCheck -check-prefixes=CHECK,UNROLL2 %s +; RUN: opt -mtriple=amdgpu12.00-amd-amdhsa -p=pre-isel-intrinsic-lowering -S < %s | FileCheck -check-prefixes=CHECK,DEFAULT %s +; RUN: opt -mtriple=amdgpu12.00-amd-amdhsa -p=pre-isel-intrinsic-lowering -S -amdgpu-memcpy-loop-unroll=2 %s -o - | FileCheck -check-prefixes=CHECK,UNROLL2 %s define void @memset_pattern_i128_len0_dynvalue(ptr align 16 %a, i128 %value) { ; CHECK-LABEL: @memset_pattern_i128_len0_dynvalue( diff --git a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll index faee9f95ebdac..71592148f3ebc 100644 --- a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll +++ b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expamd-masked-load.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s +; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgpu-amd-amdhsa | FileCheck %s ; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar, ; COM: since, on GPUs, each i1 takes up at least one register and so they should diff --git a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll index 8c4408bfa527b..511275f7bacc9 100644 --- a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll +++ b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-gather.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s +; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgpu-amd-amdhsa | FileCheck %s ; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar, ; COM: since, on GPUs, each i1 takes up at least one register and so they should diff --git a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll index 448ee18e9b4de..efd56eb532e01 100644 --- a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll +++ b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-scatter.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s +; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgpu-amd-amdhsa | FileCheck %s ; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar, ; COM: since, on GPUs, each i1 takes up at least one register and so they should diff --git a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-store.ll b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-store.ll index 2eb86f20374d8..bc335937292f4 100644 --- a/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-store.ll +++ b/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AMDGPU/expand-masked-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s +; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgpu-amd-amdhsa | FileCheck %s ; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar, ; COM: since, on GPUs, each i1 takes up at least one register and so they should diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll index 0d21a99153ea0..fe74d833b259f 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -passes=separate-const-offset-from-gep -S | FileCheck %s +; RUN: opt < %s -mtriple=amdgpu12.00-amd-amdhsa -passes=separate-const-offset-from-gep -S | FileCheck %s ; gfx1200 is particularly interesting since it allows negative immediate offsets ; in flat instructions, so the transformation is applied in more cases. diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll index 46535370a20e2..8cb684538cb35 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -mtriple=amdgcn-- -S -passes=separate-const-offset-from-gep,gvn -reassociate-geps-verify-no-dead-code < %s | FileCheck -check-prefix=IR %s +; RUN: opt -mtriple=amdgpu-- -S -passes=separate-const-offset-from-gep,gvn -reassociate-geps-verify-no-dead-code < %s | FileCheck -check-prefix=IR %s @array = internal addrspace(4) constant [4096 x [32 x float]] zeroinitializer, align 4 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
