================
@@ -71,3 +71,106 @@ def LXWU_S_UW : ScaledIndexLoad<0b101, 0b10, 1,
"lxwu.s.uw">, Sched<[WriteLDW, R
def LXD_S : ScaledIndexLoad<0b100, 0b11, 0, "lxd.s">, Sched<[WriteLDD,
ReadMemBase, ReadMemBase]>;
def LXD_S_UW : ScaledIndexLoad<0b101, 0b11, 0, "lxd.s.uw">, Sched<[WriteLDD,
ReadMemBase, ReadMemBase]>;
} // Predicates = [HasStdExtZilx, IsRV64]
+
+class AddrRegReg<int N>
+ : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">">;
+class AddrRegZextReg<int N>
+ : ComplexPattern<i64, 2, "SelectAddrRegZextRegFixedScale<"#N#", 32>",
+ [], [], 10>;
+
+def AddrRegReg0 : AddrRegReg<0>;
+def AddrRegReg1 : AddrRegReg<1>;
+def AddrRegReg2 : AddrRegReg<2>;
+def AddrRegReg3 : AddrRegReg<3>;
+
+def AddrRegZextReg0 : AddrRegZextReg<0>;
+def AddrRegZextReg1 : AddrRegZextReg<1>;
+def AddrRegZextReg2 : AddrRegZextReg<2>;
+def AddrRegZextReg3 : AddrRegZextReg<3>;
+
+let AddedComplexity = 2 in {
----------------
wangpc-pp wrote:
AddedComplexity is needed so we can select Zilx. I haven't investigated the
reason and I will try to explain it.
https://github.com/llvm/llvm-project/pull/209420
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