================
@@ -34,6 +34,28 @@ using namespace llvm;
#define DEBUG_TYPE "gcn-vopd-utils"
+// Check if physical register from src<SrcIdx> operand of MI<CompIdx> matches
+// register class constraints in corresponding VOPDOpc operand with name
+// src/vsrc<SrcIdx><CompIdx>.
+bool isValidVOPDSrc(const SIInstrInfo &TII, int VOPDOpc, unsigned CompIdx,
+ unsigned SrcIdx, Register PhysSrcReg) {
+ using namespace AMDGPU;
+ static constexpr OpName OpNames[] = {
+ OpName::src0X, OpName::vsrc1X, OpName::vsrc2X, OpName::src2X,
+ OpName::src0Y, OpName::vsrc1Y, OpName::vsrc2Y, OpName::src2Y};
+ unsigned OpNamesIdx = CompIdx * 4 + SrcIdx; // 4 possible OpNames per CompIdx
+ unsigned OpNamesCnt = SrcIdx == 2 ? 2 : 1; // src2 has 2 possible OpNames
+
+ int OpIdx = -1;
+ for (unsigned I = OpNamesIdx; I != OpNamesIdx + OpNamesCnt; ++I) {
+ OpIdx = getNamedOperandIdx(VOPDOpc, OpNames[I]);
+ if (OpIdx > 0)
+ break;
+ }
+
+ return TII.getRegClass(TII.get(VOPDOpc), OpIdx)->contains(PhysSrcReg);
----------------
mbrkusanin wrote:
`assert(OpIdx != -1)` before this
https://github.com/llvm/llvm-project/pull/196515
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
