https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/217323
None >From e8ea45729f94b07b83143485e3dd02c38e54749b Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Wed, 19 Aug 2026 17:25:25 +0530 Subject: [PATCH] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM --- llvm/lib/Target/AMDGPU/AMDGPU.h | 15 ++- llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 3 +- .../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 92 +++++++++++++------ .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +- .../combine-redundant-sext-inreg.mir | 1 + .../combine-sext-trunc-sextinreg.mir | 1 + .../GlobalISel/combine-shift-amount-zext.mir | 1 + .../AMDGPU/GlobalISel/combine-trunc-sext.mir | 1 + .../regbankcombiner-clamp-fmed3-const.mir | 2 + .../regbankcombiner-clamp-minmax-const.mir | 1 + .../regbankcombiner-fmed3-minmax-const.mir | 1 + .../regbankcombiner-ignore-copies-crash.mir | 1 + .../regbankcombiner-merge-readanylane.mir | 1 + .../regbankcombiner-redundant-and.mir | 1 + .../GlobalISel/regbankcombiner-smed3.mir | 2 + .../GlobalISel/regbankcombiner-umed3.mir | 2 + 16 files changed, 97 insertions(+), 32 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index ec510fa2ba67e..9d9dda8a7e23f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -36,8 +36,19 @@ class AMDGPUPreLegalizerCombinerPass }; void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); -FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone); -void initializeAMDGPURegBankCombinerPass(PassRegistry &); +FunctionPass *createAMDGPURegBankCombinerLegacy(bool IsOptNone); +void initializeAMDGPURegBankCombinerLegacyPass(PassRegistry &); + +class AMDGPURegBankCombinerPass + : public RequiredPassInfoMixin<AMDGPURegBankCombinerPass> { + bool IsOptNone; + +public: + explicit AMDGPURegBankCombinerPass(bool IsOptNone = false); + + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass(); class AMDGPUGlobalISelDivergenceLoweringPass diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 32cb229d0b975..9f37a71f932fe 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -132,6 +132,7 @@ MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner", AMDGPUPreLegalizerCombinerPass()) MACHINE_FUNCTION_PASS("amdgpu-regbankselect", AMDGPURegBankSelectPass()) MACHINE_FUNCTION_PASS("amdgpu-regbanklegalize", AMDGPURegBankLegalizePass()) +MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass()) MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass()) MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass()) MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) @@ -168,6 +169,4 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass()) // Global ISel passes DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner", AMDGPUPostLegalizerCombinerPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass()) - #undef DUMMY_MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index e218bdd826bab..af781887a60f8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -24,6 +24,8 @@ #include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionAnalysisManager.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/Target/TargetMachine.h" @@ -627,14 +629,35 @@ bool AMDGPURegBankCombinerImpl::isClampZeroToOne(MachineInstr *K0, return false; } +static bool runCombiner(MachineFunction &MF, GISelValueTracking &VT, + MachineDominatorTree *MDT, + const AMDGPURegBankCombinerImplRuleConfig &RuleConfig, + bool EnableOpt) { + const Function &F = MF.getFunction(); + const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); + const auto *LI = ST.getLegalizerInfo(); + + CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, + LI, EnableOpt, F.hasOptSize(), F.hasMinSize()); + // Disable fixed-point iteration to reduce compile-time + CInfo.MaxIterations = 1; + CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; + // RegBankSelect seems not to leave dead instructions, so a full DCE pass is + // unnecessary. + CInfo.EnableFullDCE = false; + AMDGPURegBankCombinerImpl Impl(MF, CInfo, VT, /*CSEInfo*/ nullptr, RuleConfig, + ST, MDT, LI); + return Impl.combineMachineInstrs(); +} + // Pass boilerplate // ================ -class AMDGPURegBankCombiner : public MachineFunctionPass { +class AMDGPURegBankCombinerLegacy : public MachineFunctionPass { public: static char ID; - AMDGPURegBankCombiner(bool IsOptNone = false); + AMDGPURegBankCombinerLegacy(bool IsOptNone = false); StringRef getPassName() const override { return "AMDGPURegBankCombiner"; } @@ -648,7 +671,7 @@ class AMDGPURegBankCombiner : public MachineFunctionPass { }; } // end anonymous namespace -void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { +void AMDGPURegBankCombinerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); AU.addRequired<GISelValueTrackingAnalysisLegacy>(); @@ -659,50 +682,67 @@ void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); } -AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone) +AMDGPURegBankCombinerLegacy::AMDGPURegBankCombinerLegacy(bool IsOptNone) : MachineFunctionPass(ID), IsOptNone(IsOptNone) { if (!RuleConfig.parseCommandLineOption()) report_fatal_error("Invalid rule identifier"); } -bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) { +bool AMDGPURegBankCombinerLegacy::runOnMachineFunction(MachineFunction &MF) { if (MF.getProperties().hasFailedISel()) return false; const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); - GISelValueTracking *VT = - &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF); - - const auto *LI = ST.getLegalizerInfo(); + GISelValueTracking &VT = + getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF); MachineDominatorTree *MDT = IsOptNone ? nullptr : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, - LI, EnableOpt, F.hasOptSize(), F.hasMinSize()); - // Disable fixed-point iteration to reduce compile-time - CInfo.MaxIterations = 1; - CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; - // RegBankSelect seems not to leave dead instructions, so a full DCE pass is - // unnecessary. - CInfo.EnableFullDCE = false; - AMDGPURegBankCombinerImpl Impl(MF, CInfo, *VT, /*CSEInfo*/ nullptr, - RuleConfig, ST, MDT, LI); - return Impl.combineMachineInstrs(); + return runCombiner(MF, VT, MDT, RuleConfig, EnableOpt); } -char AMDGPURegBankCombiner::ID = 0; -INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE, +char AMDGPURegBankCombinerLegacy::ID = 0; +INITIALIZE_PASS_BEGIN(AMDGPURegBankCombinerLegacy, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) -INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE, +INITIALIZE_PASS_END(AMDGPURegBankCombinerLegacy, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) -FunctionPass *llvm::createAMDGPURegBankCombiner(bool IsOptNone) { - return new AMDGPURegBankCombiner(IsOptNone); +FunctionPass *llvm::createAMDGPURegBankCombinerLegacy(bool IsOptNone) { + return new AMDGPURegBankCombinerLegacy(IsOptNone); +} + +AMDGPURegBankCombinerPass::AMDGPURegBankCombinerPass(bool IsOptNone) + : IsOptNone(IsOptNone) {} + +PreservedAnalyses +AMDGPURegBankCombinerPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (MF.getProperties().hasFailedISel()) + return PreservedAnalyses::all(); + + AMDGPURegBankCombinerImplRuleConfig RuleConfig; + if (!RuleConfig.parseCommandLineOption()) + report_fatal_error("Invalid rule identifier"); + + const Function &F = MF.getFunction(); + bool EnableOpt = + MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !F.hasOptNone(); + + GISelValueTracking &VT = MFAM.getResult<GISelValueTrackingAnalysis>(MF); + MachineDominatorTree *MDT = + IsOptNone ? nullptr : &MFAM.getResult<MachineDominatorTreeAnalysis>(MF); + + if (!runCombiner(MF, VT, MDT, RuleConfig, EnableOpt)) + return PreservedAnalyses::all(); + + PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses(); + PA.preserveSet<CFGAnalyses>(); + PA.preserve<GISelValueTrackingAnalysis>(); + return PA; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 7397e8c7f8a30..4807f99abd8f2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -701,7 +701,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(*PR); initializeAMDGPUPostLegalizerCombinerPass(*PR); initializeAMDGPUPreLegalizerCombinerLegacyPass(*PR); - initializeAMDGPURegBankCombinerPass(*PR); + initializeAMDGPURegBankCombinerLegacyPass(*PR); initializeAMDGPUPromoteAllocaPass(*PR); initializeAMDGPUCodeGenPreparePass(*PR); initializeAMDGPULateCodeGenPrepareLegacyPass(*PR); @@ -1797,7 +1797,7 @@ bool GCNPassConfig::addRegBankSelect() { void GCNPassConfig::addPreGlobalInstructionSelect() { bool IsOptNone = getOptLevel() == CodeGenOptLevel::None; - addPass(createAMDGPURegBankCombiner(IsOptNone)); + addPass(createAMDGPURegBankCombinerLegacy(IsOptNone)); } bool GCNPassConfig::addGlobalInstructionSelect() { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir index e5d3ea7fc2d3d..322d9644ab12b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: inreg8_inreg16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir index c6dcbfdef8493..eafb546ff25ca 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # Check (sext (trunc (sext_inreg x))) can be folded, as it's a pattern that can arise when # CGP widening of uniform i16 ops is disabled. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir index 5b4e5853be124..7faa15babab66 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: lshr_zext_i16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir index eb5f2f7f24cd5..eb3d1fd77dbbc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s # RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s --- name: trunc_sext_i32_i16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir index 66777e26cd495..695b645f2f869 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=GFX12 +# RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --check-prefix=GFX12 --- name: test_fmed3_f32_known_nnan_ieee_true legalized: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir index 277a6016e5bf6..35e71aeeae33f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: test_min_max_ValK0_K1_f32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir index 580171ea27244..276fe667c498c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: test_min_max_ValK0_K1_f32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir index a0081a58f2488..7becd9c99b160 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # COM: Check that the pass doesn't crash. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir index e39604cb12a87..17c35c51d4b41 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -run-pass=amdgpu-regbank-combiner %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -passes=amdgpu-regbank-combiner %s -verify-each -o - | FileCheck %s --- name: readanylane_and_uniform_merge_to_virtual_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir index f0e747be99ab3..658e821ab62d5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: replaceRegWith_requires_copy diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir index 5809810e01253..5ce78b90441f8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: test_min_max_ValK0_K1_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir index b63b38af1856a..9c5b08efa3d6d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: test_min_max_ValK0_K1_u32 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
