https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/217323
>From 33228b60cb006350cf829663592c79a7cd3de326 Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Wed, 19 Aug 2026 17:25:25 +0530 Subject: [PATCH] [AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM --- llvm/lib/Target/AMDGPU/AMDGPU.h | 15 ++- llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 3 +- .../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 113 +++++++++++++----- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +- .../regbankcombiner-clamp-fmed3-const.mir | 2 + .../regbankcombiner-merge-readanylane.mir | 1 + .../GlobalISel/regbankcombiner-smed3.mir | 2 + 7 files changed, 102 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index ec510fa2ba67e..9d9dda8a7e23f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -36,8 +36,19 @@ class AMDGPUPreLegalizerCombinerPass }; void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); -FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone); -void initializeAMDGPURegBankCombinerPass(PassRegistry &); +FunctionPass *createAMDGPURegBankCombinerLegacy(bool IsOptNone); +void initializeAMDGPURegBankCombinerLegacyPass(PassRegistry &); + +class AMDGPURegBankCombinerPass + : public RequiredPassInfoMixin<AMDGPURegBankCombinerPass> { + bool IsOptNone; + +public: + explicit AMDGPURegBankCombinerPass(bool IsOptNone = false); + + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass(); class AMDGPUGlobalISelDivergenceLoweringPass diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 00e27ed416a50..546a864863991 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -132,6 +132,7 @@ MACHINE_FUNCTION_PASS("amdgpu-prelegalizer-combiner", AMDGPUPreLegalizerCombinerPass()) MACHINE_FUNCTION_PASS("amdgpu-reg-bank-select", AMDGPURegBankSelectPass()) MACHINE_FUNCTION_PASS("amdgpu-reg-bank-legalize", AMDGPURegBankLegalizePass()) +MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass()) MACHINE_FUNCTION_PASS("amdgpu-preload-kern-arg-prolog", AMDGPUPreloadKernArgPrologPass()) MACHINE_FUNCTION_PASS("amdgpu-prepare-agpr-alloc", AMDGPUPrepareAGPRAllocPass()) MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) @@ -168,6 +169,4 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass()) // Global ISel passes DUMMY_MACHINE_FUNCTION_PASS("amdgpu-postlegalizer-combiner", AMDGPUPostLegalizerCombinerPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-regbank-combiner", AMDGPURegBankCombinerPass()) - #undef DUMMY_MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index e218bdd826bab..310e0018af024 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -24,6 +24,8 @@ #include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionAnalysisManager.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/Target/TargetMachine.h" @@ -627,14 +629,42 @@ bool AMDGPURegBankCombinerImpl::isClampZeroToOne(MachineInstr *K0, return false; } +static bool runCombiner(MachineFunction &MF, + function_ref<GISelValueTracking *()> GetVT, + function_ref<MachineDominatorTree *()> GetMDT, + const AMDGPURegBankCombinerImplRuleConfig &RuleConfig, + bool EnableOpt) { + if (MF.getProperties().hasFailedISel()) + return false; + + const Function &F = MF.getFunction(); + const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); + const auto *LI = ST.getLegalizerInfo(); + + CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, + LI, EnableOpt, F.hasOptSize(), F.hasMinSize()); + // Disable fixed-point iteration to reduce compile-time + CInfo.MaxIterations = 1; + CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; + // RegBankSelect seems not to leave dead instructions, so a full DCE pass is + // unnecessary. + CInfo.EnableFullDCE = false; + + GISelValueTracking *VT = GetVT(); + MachineDominatorTree *MDT = GetMDT(); + AMDGPURegBankCombinerImpl Impl(MF, CInfo, *VT, /*CSEInfo*/ nullptr, + RuleConfig, ST, MDT, LI); + return Impl.combineMachineInstrs(); +} + // Pass boilerplate // ================ -class AMDGPURegBankCombiner : public MachineFunctionPass { +class AMDGPURegBankCombinerLegacy : public MachineFunctionPass { public: static char ID; - AMDGPURegBankCombiner(bool IsOptNone = false); + AMDGPURegBankCombinerLegacy(bool IsOptNone = false); StringRef getPassName() const override { return "AMDGPURegBankCombiner"; } @@ -648,7 +678,7 @@ class AMDGPURegBankCombiner : public MachineFunctionPass { }; } // end anonymous namespace -void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { +void AMDGPURegBankCombinerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); AU.addRequired<GISelValueTrackingAnalysisLegacy>(); @@ -659,50 +689,69 @@ void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); } -AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone) +AMDGPURegBankCombinerLegacy::AMDGPURegBankCombinerLegacy(bool IsOptNone) : MachineFunctionPass(ID), IsOptNone(IsOptNone) { if (!RuleConfig.parseCommandLineOption()) report_fatal_error("Invalid rule identifier"); } -bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasFailedISel()) - return false; +bool AMDGPURegBankCombinerLegacy::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); - GISelValueTracking *VT = - &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF); - - const auto *LI = ST.getLegalizerInfo(); - MachineDominatorTree *MDT = - IsOptNone ? nullptr - : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - - CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, - LI, EnableOpt, F.hasOptSize(), F.hasMinSize()); - // Disable fixed-point iteration to reduce compile-time - CInfo.MaxIterations = 1; - CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; - // RegBankSelect seems not to leave dead instructions, so a full DCE pass is - // unnecessary. - CInfo.EnableFullDCE = false; - AMDGPURegBankCombinerImpl Impl(MF, CInfo, *VT, /*CSEInfo*/ nullptr, - RuleConfig, ST, MDT, LI); - return Impl.combineMachineInstrs(); + return runCombiner( + MF, + [&]() { + return &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF); + }, + [&]() -> MachineDominatorTree * { + return IsOptNone ? nullptr + : &getAnalysis<MachineDominatorTreeWrapperPass>() + .getDomTree(); + }, + RuleConfig, EnableOpt); } -char AMDGPURegBankCombiner::ID = 0; -INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE, +char AMDGPURegBankCombinerLegacy::ID = 0; +INITIALIZE_PASS_BEGIN(AMDGPURegBankCombinerLegacy, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) -INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE, +INITIALIZE_PASS_END(AMDGPURegBankCombinerLegacy, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) -FunctionPass *llvm::createAMDGPURegBankCombiner(bool IsOptNone) { - return new AMDGPURegBankCombiner(IsOptNone); +FunctionPass *llvm::createAMDGPURegBankCombinerLegacy(bool IsOptNone) { + return new AMDGPURegBankCombinerLegacy(IsOptNone); +} + +AMDGPURegBankCombinerPass::AMDGPURegBankCombinerPass(bool IsOptNone) + : IsOptNone(IsOptNone) {} + +PreservedAnalyses +AMDGPURegBankCombinerPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + AMDGPURegBankCombinerImplRuleConfig RuleConfig; + if (!RuleConfig.parseCommandLineOption()) + reportFatalUsageError("Invalid rule identifier"); + + const Function &F = MF.getFunction(); + bool EnableOpt = + MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !F.hasOptNone(); + + if (!runCombiner( + MF, [&]() { return &MFAM.getResult<GISelValueTrackingAnalysis>(MF); }, + [&]() -> MachineDominatorTree * { + return IsOptNone + ? nullptr + : &MFAM.getResult<MachineDominatorTreeAnalysis>(MF); + }, + RuleConfig, EnableOpt)) + return PreservedAnalyses::all(); + + PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses(); + PA.preserveSet<CFGAnalyses>(); + PA.preserve<GISelValueTrackingAnalysis>(); + return PA; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index e5a681b95f88e..245c919e6b4e3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -715,7 +715,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(*PR); initializeAMDGPUPostLegalizerCombinerPass(*PR); initializeAMDGPUPreLegalizerCombinerLegacyPass(*PR); - initializeAMDGPURegBankCombinerPass(*PR); + initializeAMDGPURegBankCombinerLegacyPass(*PR); initializeAMDGPUPromoteAllocaPass(*PR); initializeAMDGPUCodeGenPreparePass(*PR); initializeAMDGPULateCodeGenPrepareLegacyPass(*PR); @@ -1811,7 +1811,7 @@ bool GCNPassConfig::addRegBankSelect() { void GCNPassConfig::addPreGlobalInstructionSelect() { bool IsOptNone = getOptLevel() == CodeGenOptLevel::None; - addPass(createAMDGPURegBankCombiner(IsOptNone)); + addPass(createAMDGPURegBankCombinerLegacy(IsOptNone)); } bool GCNPassConfig::addGlobalInstructionSelect() { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir index 66777e26cd495..695b645f2f869 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=GFX12 +# RUN: llc -mtriple=amdgpu12.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --check-prefix=GFX12 --- name: test_fmed3_f32_known_nnan_ieee_true legalized: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir index e39604cb12a87..17c35c51d4b41 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -run-pass=amdgpu-regbank-combiner %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -passes=amdgpu-regbank-combiner %s -verify-each -o - | FileCheck %s --- name: readanylane_and_uniform_merge_to_virtual_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir index 5809810e01253..5ce78b90441f8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s # RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10-amd-mesa3d -passes=amdgpu-regbank-combiner -verify-each %s -o - | FileCheck %s --- name: test_min_max_ValK0_K1_i32 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
