https://bugs.llvm.org/show_bug.cgi?id=39324
Bug ID: 39324
Summary: [AMDGPU][MC][GFX9] Incorrect VAddr size for
image_sample_b and image_sample_b_o with a16=1
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: unassignedb...@nondot.org
Reporter: dpreobrazhen...@luxoft.com
CC: llvm-bugs@lists.llvm.org
According to AMD doc, image_sample_b has the following address components:
- bias;
- at least one coordinate (1D).
Both components may be packed, so in case of a16=1 all address components fit
into one register:
image_sample_b v5, v1, s[8:15], s[12:15] dmask:0x1 a16
This looks like a valid code. However assembler expects at least 64-bit VAddr:
image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
A similar problem exists with image_sample_b_o. These two are the only GFX9
instructions which have issues with VAddr size.
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