| Issue |
61430
|
| Summary |
[GlobalISel][AMDGPU] machine verify error: VOP* instruction violates constant bus restriction
|
| Labels |
globalisel
|
| Assignees |
|
| Reporter |
chenzheng1030
|
This is from https://reviews.llvm.org/D141247, with that patch, there are some AMDGPU cases crash because of machine verify error. Below is a reduced case from `llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir`.
To reproduce this error, first need to do some change in the td file:
```
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 70e50111790b..80d95fb0ad01 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -263,7 +263,7 @@ let SchedRW = [Write64Bit] in {
def : GCNPat<
(i32 (DivergentUnaryFrag<sext> i16:$src)),
- (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
+ (i32 (V_BFE_I32_e64 i16:$src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
>;
```
And then we get LIT failure for case `llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir`:
```
# After InstructionSelect
# Machine code for function zext_vgpr_s1_to_vgpr_s16: IsSSA, NoPHIs, Legalized, RegBankSelected, Selected
bb.0:
%0:vgpr_32 = COPY $vgpr0
%2:vgpr_32 = V_AND_B32_e32 1, %0:vgpr_32, implicit $exec
%5:sreg_32 = S_MOV_B32 16
%4:sreg_32 = S_MOV_B32 0
%3:vgpr_32 = V_BFE_I32_e64 %2:vgpr_32, %4:sreg_32, %5:sreg_32, implicit $exec
$vgpr0 = COPY %3:vgpr_32
# End machine code for function zext_vgpr_s1_to_vgpr_s16.
*** Bad machine code: VOP* instruction violates constant bus restriction ***
- function: zext_vgpr_s1_to_vgpr_s16
- basic block: %bb.0 (0x2b23ba70)
- instruction: %3:vgpr_32 = V_BFE_I32_e64 %2:vgpr_32, %4:sreg_32, %5:sreg_32, implicit $exec
```
The error can also be reproduced with below mir source:
```
name: zext_vgpr_s1_to_vgpr_s16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s16) = G_ZEXT %1
%3:vgpr(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
```
```
llc -march=amdgcn -run-pass=instruction-select -global-isel inst-select-zext.mir -verify-machineinstrs
```
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