| Issue |
61431
|
| Summary |
[AArch64][CodeGen]: LD{AX}P/S{LX}TP endian swap
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
lukeg101
|
Consider the following code (https://godbolt.org):
```
volatile __int128 a;
a = 1;
```
which emits a store pair on AArch64 when compiled to target a big-endian system:
```
stp x9, xzr, [x8]
```
such that the contents of x9 (containing 1) are stored in the lower 64-bits, and zero is stored in the higher 64-bits. This means the order that data is stored is flipped on a big endian system.
Removing `volatile` in the above example flips the order bits are stored for big-endian:
```
stp xzr, x9, [x8]
```
likewise marking `a` as `_Atomic` acts like `volatile` as it is marked as volatile internally by LLVM (https://godbolt.org/z/osT1Wfez5):
```
stp x9, xzr, [x8]
```
According to the Arm pseudocode (https://developer.arm.com/documentation/ddi0596/2021-06/Base-Instructions/STP--Store-Pair-of-Registers-) the order in which the 128-bits is stored is flipped only if the access type is not `BigEndian(AccType_NORMAL)`.
Further this seems to effect load-acquire-exclusive and store-release exclusive pairs in compare and swap loops too (https://godbolt.org/z/7fjMxvoE7):
```
.LBB0_1: // =>This Inner Loop Header: Depth=1
ldaxp xzr, x10, [x9]
stlxp w10, x8, xzr, [x9]
cbnz w10, .LBB0_1
```
My understanding of this is that the endianness for big-endian systems is flipped.
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