FYI, some interesting trend information from Marcus... ------ Forwarded Message From: "W. Marcus Miller" <[EMAIL PROTECTED]> Organization: LLNL Reply-To: [EMAIL PROTECTED] Date: Wed, 23 Aug 2006 16:07:49 -0700 To: Ghaleb Abdulla <[EMAIL PROTECTED]>, Sergei Nikolaev <[EMAIL PROTECTED]>, Kem Cook <[EMAIL PROTECTED]>, Scot Olivier <[EMAIL PROTECTED]>, "John Nitao" <[EMAIL PROTECTED]> Cc: Jeffrey P Kantor <[EMAIL PROTECTED]> Subject: HotChips 2006 Highlights
Greetings, I attended HotChips again this year. I like this venue because it provides an opportunity to meet Industry and Research architects/designers/leaders in H/W architectures and implementations, plus provides a barometer on the current state-of-the art in silicon fabrication (and general health of the silicon industry). A semi-brief summary follows: Moore's Law Where have all the Gigahertz gone? IBM fellow Bernard Meyerson had some interesting observations and historical perspective on the current failure of CMOS technology to replicate another revision of Moore's Law scaling beyond 65nm and smaller feature sizes. The basic problem is that atoms don't scale :-) Once you reach a small enough feature size your leakage currents and fault rates become too high (in CMOS). To compensate for high leakage, designers are forced to increase transistor oxide thickness, which requires more current/voltage to switch, and this rapidly drives the heat beyond any level that can be dissipated (at least with air cooling). He pointed out that the same scaling failure occurred in bipolar technology in the late 1980s when IBM reached a heat density of 13 watts/cm2 (a typical steam iron has a heat density of 5 watts/cm2). This was the primary motivation for the industry shift to CMOS. The problem is, there are no alternative lower power technologies waiting in the wing like there was in 1990 (at least not for the next several years). He also showed some data that indicated for the next generation of servers, the cost of cooling and power in the machine room/datacenter will far exceed the cost of the compute H/W over a single generation (18 months). So, is Moore's Law still applicable? Yes and No. Moore's law is a statement about the number of devices that can be integrated on a fixed area every 12-18 months (doubling) for a given technology. Clearly we have exhausted CMOS clock doubling, but not the number of devices that can be fabricated on a single die, hence the industry move to multi-core. The industry is also obtaining higher yields with large die sizes. Bottom line, the next generation of chips are going to require significantly more architectural innovation to obtain higher performance levels using techniques other than just feature reduction and clock doubling. Multi-Core Both AMD and Intel announced plans for 8-way multi-core CPUs in 2007, with product shipping in 4Q 2007/1Q 2008. Intel is also prototyping a multi-core chip with 16 to 32 CPUs, a shared cache design, high B/W memory interface and several fixed function units on a single die (appears to resemble IBM Cell, but details are very sketchy). Intel's big problem seems to be the lack of a "Killer App" for the masses that will drive customers to the new chip :-) Intel also presented papers on their dual core Tulsa processor (Xeon based - to be announced next week), their Blackford dual processor chipset (the northbridge for two dual core systems - 4 CPU system), and their Core Microarchitecture. High Performance with Low Power Budgets Several vendors presented papers on high performance H/W on a power budget (PA SEMI, IBM, ARM, MIPS32). There is an interesting market developing here,as many of these devices once primarily targeted embedded systems, they are now looking more like mainstream processors. Reconfigurable Computing Xilinx presented a paper on the Vertex-5 FPGA (65 nm), David Patterson (Berkeley) described the Research Accelerator for Multiple Processors (RAMP) project and Toshiba presented a Hardware Accelerator based on a dynamically reconfigurable architecture. Vertex-5 is a bigger (1 billion transistors on a 23x23 mm substrait), faster version of Vertex-4 with a 1 volt core that still maintains 3.3v compatibility. RAMP is an effort to do H/W architecture simulation in H/W, as the next generation parallel architectures are too complex to simulate in software (at least in the designers lifetime) and only $Billion+ fabs can produce real chips these days. The basic approach is to use FPGAs to build massively parallel simulators. Toshiba's chip uses multiple PEs (4 in the current version), each PE has 8 ALU units, and each ALU is connected to a set of reconfigurable Multiplexers that allow data to be routed to/from the other ALUs and PEs. Parallel Processing H/W Several MIMD and SIMD architectures were presented. Ambric discussed their TeraOPS hardware, and UC Davis presented a paper on Hardware and Applications for An Asynchronous Array of Simple Processors (AsAP). Ambric argues that single CPUs have reached their performance scaling limits, traditional multi-core processors won't scale to big problems, and ASIC and FPGA solutions are very hard and costly to develop and debug. The Ambric chip is an Array Processor that is also reconfigurable (RAP). It supports configuration using MIMD, SIMD or hybrid access control. Their Kestrel prototype has 45 processing elements, is fabricated in 130nm technology, using 117M transistors, and each PE is clocked at 333MHz. The product offering will be clocked at 450MHz in 65nm, and provide 70 PEs (they call them brics) on a single die. I have a copy of the proceedings should you want to copy any of the papers. Regards, Marcus -- W. Marcus Miller, Ph.D. Lawrence Livermore National Laboratory Mail Stop L-560 Tel : (925) 424-4147 7000 East Avenue FAX : (925) 422-6287 Livermore, CA 94550 e-mail: [EMAIL PROTECTED] ------ End of Forwarded Message _______________________________________________ LSST-data mailing list [email protected] http://www.lsstmail.org/mailman/listinfo/lsst-data
