>> The problem with these DSP is that whatever the size of the operand, >> (8, >> 16 or 32 bits), the compiler allways use 32bit "accesses". This is due >> to the fact that these DSPs can manipulate only 32bit registers. >> Memory accesses are also only 32bit accesses. > > Despite the optimal width of memory accesses the C6x does support a load > byte (ldb) instruction (very possibly implemented in silicon as a 32-bit > read with a mask and shift to cope with the memory access constraints). > Either way, it doesn't prevent a compiler supporting a packed structure > and knowing it will have to assume it and all its members are potentially unaligned.
Many processors I know don't support 8-bit or unaligned operations. However, the compiler fakes this: e.g. loading unaligned is done by loading twice, masking and shifting into one register. Simon _______________________________________________ lwip-users mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/lwip-users
