Hi, The clock jitter is documented in ST errata. (This file is not easy to find. Instead of hiding it ST had to put it into Data Sheet and big bold letters). As far as I understand it you can not use ST PLL neither for MII not for RMII as in both cases it does not fir the long term jitter requirement for PHY. Without going deep into understanding the meaning of this bug and possible outcome we have used external 25MHz crystal with MII. (For RMII you will need 50MHz one).
As for open source, I also thought about it but ST ignorance stopped me from doing it. I think respectable company like ST has to take care on the ugly source code they provide on their web site. It is not only related to Ethernet driver but their Peripheral Library is exactly in the same state. (In my projects I do not use it at all and write my own library adding support of different HW modules as a need for it comes up). So I decided not to help them and not to disclose any code. But if you are looking for some cooperation I'm in. The final goal is to get stable driver with zero-copy. To my understanding MAC and DMA periheral of the STM32F2xx is sufficient for that. -- View this message in context: http://lwip.100.n7.nabble.com/Low-Iperf-performance-of-lwip-1-4-1-on-STM32-and-FreeRTOS-tp21579p21669.html Sent from the lwip-users mailing list archive at Nabble.com. _______________________________________________ lwip-users mailing list [email protected] https://lists.nongnu.org/mailman/listinfo/lwip-users
