I don't see anything in the code that reads the drive parameter table
other than the command to output that data. I'm guessing Brother may
have other drives with more capabilities and this is only there to tell
the host how the drive is configured.
Also I don't see anything for a second serial port in the code. What is
P7 connected to? I'd like to see some pictures since I don't have the
hardware. But looking at the CPU so far, it seems almost every pin is in
use.
;----------------------------------------------------------
;I/O ports
;Port.Bit I/O Pin# ID Function
;----------------------------------------------------------
;Port1.B0 Input Pin18 P10 CTS
;Port1.B1 Input Pin19 P11 DSR
;Port1.B2 Output Pin20 P12 RTS
;Port1.B3 Output Pin22 P13 DTR
;Port1.B4 Output Pin23 P14 Alarm
;Port1.B5 Output Pin24 P15 WC on R/W module
;Port1.B6 Output Pin25 P16 Drives LED1
;Port1.B7 Output Pin26 P17 Scan
;Port2.B0 Output Pin11 P20 Serial Output enable, Mode
(pulled Low)
;Port2.B1 Input Pin12 P21 Mode (pulled Hi)
;Port2.B2 Input Pin13 P22 (SCI) CLKOUT from CPLD for BAUD
rate (start Hi)
;Port2.B3 Input Pin14 P23 (SCI) /RXD
;Port2.B4 Output Pin15 P24 (SCI) /TXD
;Port2.B5 N/A
;Port2.B6 N/A
;Port2.B7 N/A
;Port3.B0 I/O Pin51 P30 AD0
;Port3.B1 I/O Pin50 P31 AD1
;Port3.B2 I/O Pin45 P32 AD2
;Port3.B3 I/O Pin44 P33 AD3
;Port3.B4 I/O Pin43 P34 AD4
;Port3.B5 I/O Pin42 P35 AD5
;Port3.B6 I/O Pin41 P36 AD6
;Port3.B7 I/O Pin40 P37 AD7
;Port4.B0 I/O Pin37 P40 A8
;Port4.B1 I/O Pin36 P41 A9
;Port4.B2 I/O Pin35 P42 A10
;Port4.B3 Input Pin32 P43 A11 E1 *Config jumper pulled hi
;Port4.B4 Input Pin31 P44 A12 E2 *Config jumper pulled hi
;Port4.B5 Input Pin30 P45 A13 E3 *Config jumper pulled hi
;Port4.B6 I/O Pin29 P46 A14 *CS1 on CPLD
;Port4.B7 I/O Pin28 P47 A15 *CS0 on CPLD
On 1/28/24 08:21, Stephen Adolph wrote:
Thanks Darren.
Now that we have the real tpdd firmware I wonder what we can do with
it. Some of those variables look tempting, like side and # of tracks.
Another question.. it looks like was there a second unpopulated serial
port on the drive? Anything in the code on that?
P7 is unpopulated and not in the schematic, but it is there.
Steve
On Sunday, January 28, 2024, Darren Clark <[email protected]> wrote:
Spent some time digging through the source of the TPDD2 firmware,
adding comments, labels, and variable names.
It's documented (as far as I got so far) here:
https://github.com/BiggRanger/Tandy_PDD/blob/master/PDD2.ASM
Doesn't look like any hidden commands exist in the firmware. This
is the list from the command table at 0xFFB9:
code 0xF230 Command_FMT00_CreateDirectory
code 0xF4D0 Command_FMT01_FileOpen
code 0xF495 Command_FMT02_FileClose
code 0xF69D Command_FMT03_FileRead
code 0xF63D Command_FMT04_File_Write
code 0xF425 Command_FMT05_FileDelete
code 0xF212 Command_FMT06_DiskFormat
code 0xF6F3 Command_FMT07_DriveStatus
code 0xF137 Command_FMT_Invalid
code 0xF75F Command_FMT23_DriveVersionInfo
code 0xF746 Command_FMT0C_DriveCondition
code 0xF365 Command_FMT0D_FileNameChange
code 0xF801 Command_FMT30_SectorModeReadWrite
code 0xF76B Command_FMT31_DriveMemorySet
code 0xF78E Command_FMT32_DriveMemoryGet
code 0xF757 Command_FMT33_SystemVersionInfo
code 0xF7DC Command_FMT34_ExecuteProgram
Some other interesting tables are at 0xFF67 and 0xFF6D
[FF67] [80 ] [ ] Table_SysInfo: DB 0x80
;Hard sector data port address MSB
[FF68] [13 ] [ ] DB 0x13 ;Hard
sector data port address LSB
[FF69] [05 ] [ ] DB 0x05 ;Buffer size MSB
[FF6A] [00 ] [ ] DB 0x00 ;Buffer size LSB
[FF6B] [10 ] [ ] DB 0x10 ;CPU type.
0x10 = HD6301
[FF6C] [E1 ] [ ] DB 0xE1 ;Model code
[FF6D] [41 ] [A ] Table_Version: DB 0x41
;System Version Number MSB
[FF6E] [10 ] [ ] DB 0x10 ;System
Version Number LSB
[FF6F] [01 ] [ ] DB 0x01 ;Number of sides
[FF70] [00 ] [ ] DB 0x00 ;Number of
tracks MSB
[FF71] [50 ] [P ] DB 0x50 ;Number of
tracks LSB
[FF72] [05 ] [ ] DB 0x05 ;Sector length MSB
[FF73] [00 ] [ ] DB 0x00 ;Sector length LSB
[FF74] [02 ] [ ] DB 0x02 ;Sectors per track
[FF75] [00 ] [ ] DB 0x00 ;Directory
Entries MSB
[FF76] [28 ] [( ] DB 0x28 ;Directory
Entries LSB
[FF77] [00 ] [ ] DB 0x00 ;Max files
[FF78] [E1 ] [ ] DB 0xE1 ;Model code
There is also a BAUD rate table at 0xFF85, I see logic for reading
the dip switch setting from the CPLD at the program
initialization. 2 switches for the BAUD rate and the other 2 for
some other mode settings. Just a w.a.g. it almost looks like the
programming on the CPLD could be the same on the TPPD2 as the
TPPD1. It might be possible to set 9600 and 38400 BAUD, just
guessing though as I don't have any TPDD2 hardware to play with.
Overall an amazing amount of work went into this firmware. From
what I can see, it's all hand coded and has a lot of space saving
optimizations in it. Out of 4K of available space, there is only
15 bytes of unused space, and the author put his name into it
(with one byte filled with a 0xFF):
[FFDF] [***********] [ ] DB '(C) M.FUTAMURA',0xFF
;Author
Darren Clark
