Hi Kevin: Thanks a lot! This was very helpful.
Regards, Shruti On 3/13/06, Kevin Lim <[EMAIL PROTECTED]> wrote: > Hi Shruti, > > 1) To my best knowledge, the ROB, IQ, and LSQ are shared structures, > like in a normal SMT machine. You can have multiple IQ's, but that is > for clustering. The FullCPU in encumbered/cpu/full does not do register > renaming to physical registers. It renames to ROB stations by marking > registers as depending on the appropriate ROB station for its register > value. This is handled mostly through the CreateVector class, There > is only an architectural register file, and that is stored per thread. > Check cpu/exec_context.hh to see where the register file is stored. The > dependency check logic is mostly through the IQ. Check the link_idep() > function in iqueue.cc for a general idea of how the dependency chains > are created. The dispatch_one_inst() function in dispatch.cc is > probably the best way to get an overview of how the dependencies and > renaming are handled. > > 2) The FullCPU does not use any of the code from cpu/o3. Its ROB is > defined in encumbered/cpu/full/cpu.hh:376, as "class > MachineQueue<ROBStation> ROB;". You are correct that it uses the > ROBStation in encumbered/cpu/full. > > 3) You're correct. There's no place where it's explicitly stated, but > in bpred.hh:104 the BTB Entry is defined. In the code in bpred.cc, the > entire address is used for the BTB tag, as well as the entire address > for the BTB target. Thus you get 64 + 64 bits as you mentioned for the > block size. > > Hope this helps, > Kevin > > Shruti Karbhari wrote: > > >Hi all: > > > >I have been trying to understand the register renaming implementation > >in M5 but I am not very clear with it. > > > >1) I gathered from the documentation that there is a separate ROB, IQ, > >LSQ for each thread in the FullCPU. But I am not sure whether there is > >a separate implementation for the register file, register alias table > >and dependency check logic and if they are defined for individual > >threads. Can someone clarify this? > > > >2) In FullCPU, the ROB structure seems to be implemented using the > >class from cpu/o3 while the ROB entries seem to use ROBStation in > >encumbered/cpu/full. Is this right or am I missing something? > > > >3) I did not find the block size for the BTB in bpred.hh. I think it > >should be (branch address width + next branch address width i.e. 64 + > >64). Is my understanding right? > > > >Thanks & Regards, > >Shruti > > > >-- > >Shruti Karbhari > >Graduate Student > >Department of Electrical and Computer Engineering > >University of Illinois at Chicago > > > > > >------------------------------------------------------- > >This SF.Net email is sponsored by xPML, a groundbreaking scripting language > >that extends applications into web and mobile media. Attend the live webcast > >and join the prime developer group breaking into this new coding territory! > >http://sel.as-us.falkag.net/sel?cmd_______________________________________________ > >m5sim-users mailing list > >[email protected] > >https://lists.sourceforge.net/lists/listinfo/m5sim-users > > > > > > > > ------------------------------------------------------- This SF.Net email is sponsored by xPML, a groundbreaking scripting language that extends applications into web and mobile media. Attend the live webcast and join the prime developer group breaking into this new coding territory! http://sel.as-us.falkag.net/sel?cmd=lnk&kid0944&bid$1720&dat1642 _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
