Hi all: I have been trying to understand the register renaming implementation in M5 but I am not very clear with it.
1) I gathered from the documentation that there is a separate ROB, IQ, LSQ for each thread in the FullCPU. But I am not sure whether there is a separate implementation for the register file, register alias table and dependency check logic and if they are defined for individual threads. Can someone clarify this? 2) In FullCPU, the ROB structure seems to be implemented using the class from cpu/o3 while the ROB entries seem to use ROBStation in encumbered/cpu/full. Is this right or am I missing something? 3) I did not find the block size for the BTB in bpred.hh. I think it should be (branch address width + next branch address width i.e. 64 + 64). Is my understanding right? Thanks & Regards, Shruti -- Shruti Karbhari Graduate Student Department of Electrical and Computer Engineering University of Illinois at Chicago ------------------------------------------------------- This SF.Net email is sponsored by xPML, a groundbreaking scripting language that extends applications into web and mobile media. Attend the live webcast and join the prime developer group breaking into this new coding territory! http://sel.as-us.falkag.net/sel?cmd=lnk&kid0944&bid$1720&dat1642 _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
