Hi Edmond,
Unfortunately I don't know much about the sampler, so I can't help you
there, but I can give you a summary of the CPU models. Can you clarify
what you mean by CacheCPU? The two main models in M5 are the SimpleCPU
and the DetailedCPU, with more models coming in future releases. The
SimpleCPU is only a functional model that fetches, decodes, executes,
and commits instructions all in one cycle. You can configure its width
to make it a multiple IPC machine; at its default 1 width it's a 1 IPC
CPU. The DetailedCPU is an out of order model that first functionally
executes the instruction, and then sends the instruction to a timing
back-end that simulates the proper delays of going through fetch,
decode, rename, scheduling, execution, and committing. There are
several other models that are used more as utilities: the TraceCPU
drives the memory system with traces; the SamplerCPU is used to hold the
vector of CPU models to be run and switches between them.
Hope this helps.
Kevin
Edmond Coté wrote:
Hello,
I'm currently attempting to perform a full-system simulation using
M5's Sampler feature. I receive the following output after issuing "m5
switchcpu" at the command prompt:
m5.opt: m5/cpu/simple/cpu.cc:806: void SimpleCPU::tick(): Assertion
`status() == Running || status() == Idle || status() ==
DcacheMissStall' failed.
Program aborted at cycle 3967324804
The simulator is launched within m5/configs/fullsys using:
SYSTEM=Sampler MEMORY=STX NUMCPUS=4 [...] m5.opt run.py
Next, I'm not entirely clear about how the period parameter (periods =
[1e10, 200e6]) works. Am I correct to assume that the first value (in
time/ticks/??) represents the delay until the first switch to detailed
mode takes place? If so, how can I obtain a more accurate value? For
example, when set at the default value, 1e9, the simulator essentially
stalls before the CLI appears.
Finally, can anyone comment on the differences between CacheCPU and
DetailedCPU?
Thanks, your help is much appreciated.
Edmond
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