the reason we name the cpu Sampler is because we hope to eventually "sample" statistics in different periods of an application (i.e. every 1e9 cycles take 200e6 cycles of statistics).
and since the default frequency of the system is 2GHz, then yes, 2,000,000 cycles is 1ms. you can change the frequency of the processor with the FREQUENCY environment variable.
how long a sim takes depends a lot on whether you are running simple CPU, detailed CPU, full system or not, and what kind of system you are on. but running 1e9 in CPUCache to 200e6 on DetailedCPU for a network benchmark on a 3+GHz P4 takes around 3 hours or so, I believe. I don't have more specific numbers on how long detailed simulation takes, but it is pretty slow.
Lisa
On 4/4/06, Edmond Coté <[EMAIL PROTECTED]> wrote:
Thanks,
I think I got a hold of how SAMPLER works, despite the name itself is
being misleading.
A potential follow up question would be, what exactly does
root.pc_sample_interval do?
Also, what kind of simulation times can be expected for the detailed CPU
model. I'm looking at ~30s for 2,000,000 ticks, does that make sense
(Athlon X2 4800+)?, my guess is that this represents approximately 1ms
of actual time at 2GHz. Is this assumption valid?
Edmond
Lisa Hsu wrote:
> Hi Edmond,
>
> I'm not sure about the m5 switchcpu command - i've never used it before,
> hopefully someone else knows about that. but the periods that you
> mention represent how long, in cycles i believe, to run on one cpu, and
> then how long to go on the next before exiting. we currently do not
> have the capability to switch back and forth, we can only go through the
> sequence of cpus one time.
>
> if you want to change these defaults, just change the environemnet
> variable WARMUP_PERIOD and RUN_PERIOD, the same way you set SYSTEM and
> MEMORY.
>
> finally, the CacheCPU is a construct that only exists in the python
> configuration code (that is why Kevin didn't know what it was), and it's
> just a simple CPU attached to a blocking cache hierarchy.
>
> The default of our sampler is to start at a cache CPU (to warm the
> caches) for 1e9 cycles and go to a detailed CPU (to take data) for 200e6
> cycles. we also often start from a checkpoint, which we generated using
> only a simpleCPU so that we can skip a lot of the stuff that happens in
> the beginning of a program.
>
> good luck.
> lisa
>
>
> On 3/31/06, *Edmond Coté* <[EMAIL PROTECTED]
> <mailto:[EMAIL PROTECTED] >> wrote:
>
> Hello,
>
> I'm currently attempting to perform a full-system simulation using M5's
> Sampler feature. I receive the following output after issuing "m5
> switchcpu" at the command prompt:
>
> m5.opt: m5/cpu/simple/cpu.cc:806: void SimpleCPU::tick(): Assertion
> `status() == Running || status() == Idle || status() == DcacheMissStall'
> failed.
> Program aborted at cycle 3967324804
>
> The simulator is launched within m5/configs/fullsys using:
>
> SYSTEM=Sampler MEMORY=STX NUMCPUS=4 [...] m5.opt run.py
>
> Next, I'm not entirely clear about how the period parameter (periods =
> [1e10, 200e6]) works. Am I correct to assume that the first value (in
> time/ticks/??) represents the delay until the first switch to detailed
> mode takes place? If so, how can I obtain a more accurate value? For
> example, when set at the default value, 1e9, the simulator essentially
> stalls before the CLI appears.
>
> Finally, can anyone comment on the differences between CacheCPU and
> DetailedCPU?
>
> Thanks, your help is much appreciated.
>
> Edmond
>
>
>
>
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