---------- Forwarded message ----------
Date: Wed, 26 Apr 2006 13:58:55 -0400 (EDT)
From: Ronald George Dreslinski Jr <[EMAIL PROTECTED]>
To: Jos Delbar <[EMAIL PROTECTED]>
Subject: Re: [m5sim-users] Blocking buffer and MOESI coherence protocol
Although I don't see a back trace, I think the problem is coming from Line
823 of mem/cache/cache_impl.hh.
This line of code is trying to append an invalidate as a target onto the
MSHR because the request has been issued and is waiting for it's response,
but the cache has snooped someone else requesting the block. In this case
the cache needs to supply the request it saw but go directly to the
invalid state so the other cache can have ownership. This was added to
the code to support coherence with timing turned on in the bus.
The solution is to either implement the idea of targets in the
blocking_buffers, or overide the addTarget in the blocking buffers to mark
that the next state when the response comes back should be invalid (I
would also suggest putting an assert in that asserts the req being added
as a target has invalidate for the command).
Hope that helps,
-Ron
On Wed, 26 Apr 2006, Jos Delbar wrote:
Hello,
I'm getting the following error when using the MOESI coherence protocol
for my
cache hierarchy in CMP-simulations. All caches have only one MSHR and
thus use
the blocking buffer miss queue implementation.
fatal: Shouldn't call this on a blocking buffer.
@ cycle 101
[addTarget:m5/mem/cache/miss/blocking_buffer.hh, line 246]
Any idea what's happening and how to fix this? (Besides using more MSHRs
:) )
Thanks,
Jos Delbar
[EMAIL PROTECTED]
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