You can certainly do this kind of thing, but it would require hacking on
the cache model to allow it to connect to multiple busses (if I
understand your description accurately). There's almost nothing that
you can't simulate if you're willing to modify the existing cache, bus,
and coherence models (or in the extreme develop your own models), but if
you are trying to get by with just hacking the python configuration then
your choices are pretty limited.
Steve
Mishali Naik wrote:
I want to study the different nuca organizations. I am trying to
simulate the CMP NuRAPID. So I was thinking of replicating the buses and
having one bus per processor. This bus would give direct access to the
L2 to one processor only and would snoop on the other buses. For
example, for 4 cores there would be 4 buses. If you think there is a
better way of implementing this can you suggest that to me. I really do
appreciate all the help.
thanks,
Mishali
*/Steve Reinhardt <[EMAIL PROTECTED]>/* wrote:
What are you trying to accomplish? You can instantiate multiple busses
easily, but where to do it depends on why you want to do that.
Mishali Naik wrote:
> Hi All,
> I wanted to know if I can replicate the bus between the
> master interface of L1 and L2 in syscall emulation memory. If so
which
> file should I start looking at to make changes in.
> Thanks,
> Mishali
> Undergraduate Student
> UCLA
>
>
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