Hi James,

What did you modify within M5? One of those modifications may be causing the CPU to go down the wrong path and try to access a bad address. Unfortunately the CPU doesn't have many debugging statements, so it may be a bit difficult to track down if you think the error is in the CPU itself. You might want to start by turning on some trace flags to see if the instructions executed at least look correct. You can do this by using --Trace.flags="InstExec". You can also use "Bus" and "Cache" as parameters to see if the memory stream looks correct as well. If you're able to find something wrong, you can narrow down the cycles you need to look at and possibly step through the CPU with GDB or add some debugging statements yourself. There's also an option for --Trace.start=<cycle>, which helps limit the amount of output you get.

If you're running in non-full system mode, then you might be able to use the tracediff utility to compare the output of two configurations. It's in the util directory; just open it up and it has instructions inside of it (it's a short script). Generally I run this with the common option of "--Trace.flags="InstExec" -P"root.exetrace=ExecutionTrace(print_cycle=False)" " in order to compare output of two configurations. Beware that if you have interrupts or results dependent on your configuration (such as the Rpcc instruction), this may work only if your error is early on.

Sorry I don't have too much more help, I don't have much experience debugging the old CPU model either.

Kevin

James Srinivasan wrote:

I'm running a precompiled binary of gcc from SPEC2000 with the 200.i
input and a slightly modified version of m5. I find that with my
baseline configuration the benchmark completes sucessfully, however, if
I increase the cache size I get the following error:

panic: invalid addr 0x1416e0000 accessed and not misspeculating
[issue_load:m5/encumbered/cpu/full/issue.cc, line 482]

I've had a little look at issue.cc but aren't much the wiser, any advice
on how to proceed debugging? Changing the cache configuration shouldn't
change the correctness of the program I would hope.

Thanks,

James




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