I have some problem when I add a real memory controller to M5.
I think this is related to some bug in CPU model.
When memory latency is not uniform, something wrong for LSQ or somewhere.
warn: Entering event queue. Starting simulation...
37 jh3: best match jh1 sim. = 0.82514
panic: invalid addr 0x140f9e018 accessed and not misspeculating
@ cycle 27952114
I think this is related to some bug in CPU model.
When memory latency is not uniform, something wrong for LSQ or somewhere.
warn: Entering event queue. Starting simulation...
37 jh3: best match jh1 sim. = 0.82514
panic: invalid addr 0x140f9e018 accessed and not misspeculating
@ cycle 27952114
On 5/10/06,
Steve Reinhardt <[EMAIL PROTECTED]> wrote:
It's true that changing the cache size shouldn't change the correct-path
instruction sequence, but it will change the misspeculation behavior.
One possibility is that it's a misspeculated instruction and the bug is
that it isn't being recognized as such.
I second Kevin's recommendation to use tracediff on the original and
modified versions to track this down. Note that there are several
additional options besides print_cycle=False that you can use to control
the exetrace output; see python/m5/objects/ExeTrace.py. The
"speculative" and "cpseq" flags might be useful to you as well (assuming
cpseq still works... I don't think we use it that much).
Steve
James Srinivasan wrote:
> I'm running a precompiled binary of gcc from SPEC2000 with the 200.i
> input and a slightly modified version of m5. I find that with my
> baseline configuration the benchmark completes sucessfully, however, if
> I increase the cache size I get the following error:
>
> panic: invalid addr 0x1416e0000 accessed and not misspeculating
> [issue_load:m5/encumbered/cpu/full/issue.cc, line 482]
>
> I've had a little look at issue.cc but aren't much the wiser, any advice
> on how to proceed debugging? Changing the cache configuration shouldn't
> change the correctness of the program I would hope.
>
> Thanks,
>
> James
>
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