Hi Patrick,
Thanks for the heads up on this issue... it is pretty subtle. I believe
the problem you're having is actually in the detailed CPU model and not
in the ISA description language itself. If you put Rb in the memory
access code, you'll see that the Ldo::MemAcc constructor properly adds
it as a source dependence to the memory access sub-instruction.
The issue is that the detailed CPU's LSQ doesn't expect the MemAcc to
need to read any registers other than the store data operand. There's a
comment to this effect in load_store_queue::add_impl, though there's no
assertion there to validate that. The assertion you're running into is
looking at it from the other side: if you satisfy a register input
dependence of a memory access operation it asserts that you must be
satisfying the data input of a store. That's why you don't run into the
assertion failure if Rb comes out of the reg file rather than being
forwarded.
It's possible that having Rb in the memory access even works if you just
take that assertion out... though obviously since that wasn't what we
had in mind when we wrote the code, I'd want to double check that before
relying on it. Your solution of using EA is better anyway.
Steve
Patrick Meredith wrote:
There is a small issue with adding instructions to the isa relating to
the fact that loads and stores have the effective address
computation separated from the memory access. This took me a few hours
to debug because the error it causes
seems to have nothing to do with the problem, I declared an instruction
like this:
format LoadOrPrefetch {
.........
0x01: ldo({{ EA = Rb + disp; }}, {{ Ra.uq = (Mem.ul | Rb<63:32>);}});
}
The bug you run into is the assertion in load_store_queue::writeback
that the instruction isn't a store. At first glance
the above code seems like it should work. The problem is that the
memory access now requires a register operand.
The worst part is this seems to work correctly on programs where the use
of Rb is far enough away from the creation
that it gets the Rb from the register file (at least that's my theory
for why it only crashes on some tests). Fixing the code
to do the same thing and not break:
format LoadOrPrefetch {
.........
0x01: ldo({{ EA = Rb + disp; }}, {{ Ra.uq = (Mem.ul | EA<63:32>);}});
}
So the point of all this is I think a small note on this should be added
to the isa description documentation to alert others
to this potential pitfall (maybe even including the above example).
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