Hi Ali,
Thanks for your reply. I'll try it later. And I think that I have found the
reason
of the too small io access latency. Either rpcc or my own pseudo instrucion has
the
same problem. The value it returns is the cycles when the instruction is
dispatched,
not the cycles when it is written back. So, the fake dependency register does
not take
effect. The table shows the cycles of instruction execution stage of the
following
instrucion sequence.
rpcc r9,r9
...
ldl r0,0(r16)
...
rpcc r1,r1
...
_____________________________________________________________
| |rpcc r9,r9 | ldl r0,0(r16) | rpcc r1,r1 |
-------------------------------------------------------------
|fetech | 80386 | 80390 | 80395 |
-------------------------------------------------------------
|dispatch | 80402 | 80406 | 80411 |
-------------------------------------------------------------
|writeback | 80407 | 81970 | 81976 |
-------------------------------------------------------------
|commit | 80441 | 81971 | 81982 |
-------------------------------------------------------------
The values in the table are the lowest 5 digits of cycle. The remainning digits
are same.
The values come from a trace file.
Though I know the reason, I still have no idea to implement the rpcc in the
correct way.
How can I let the rpcc to get cycles when the dependency register has been
ready? Can you
give me a suggestion?
Thanks!
Richard R. Zhang
2006-05-17
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