Hi Richard, Sorry for not responding earlier. What you're encountering is one of the deficincies of the encumbered FullCPU. Like SimpleScalar, it executes instructions at the front of the pipeline instead of the execute stage. The call to execute the instruction happens in fetch.cc:880. Thus your pseudo instruction executes and returns the curTick around the time it is fetched, instead of when it writes back. We have an out of order model that executes at execute that will be included in our 2.0 release. If you can't wait until then, I suggest trying to make the front end halt and not execute until the back end drains whenever it encounters your pseudo instruction. As a start you could add an extra flag to your pseudo instruction to mark it as such (add to StaticInst, and in isa_desc), and have the code in fetch.cc detect your pseudo instruction. I'm not familiar enough with the rest of the CPU code to help you too much beyond that unfortunately. This method might be somewhat complex, and might be inaccurate by a few cycles because it waits for the pipeline to drain, but it should be closer to the real I/O latency than is currently reported.
Kevin Richard R. Zhang wrote: >Hi Ali, >Thanks for your reply. I'll try it later. And I think that I have found the >reason >of the too small io access latency. Either rpcc or my own pseudo instrucion >has the >same problem. The value it returns is the cycles when the instruction is >dispatched, >not the cycles when it is written back. So, the fake dependency register does >not take >effect. The table shows the cycles of instruction execution stage of the >following >instrucion sequence. > rpcc r9,r9 > ... > ldl r0,0(r16) > ... > rpcc r1,r1 > ... >_____________________________________________________________ >| |rpcc r9,r9 | ldl r0,0(r16) | rpcc r1,r1 | >------------------------------------------------------------- >|fetech | 80386 | 80390 | 80395 | >------------------------------------------------------------- >|dispatch | 80402 | 80406 | 80411 | >------------------------------------------------------------- >|writeback | 80407 | 81970 | 81976 | >------------------------------------------------------------- >|commit | 80441 | 81971 | 81982 | >------------------------------------------------------------- >The values in the table are the lowest 5 digits of cycle. The remainning >digits are same. >The values come from a trace file. > >Though I know the reason, I still have no idea to implement the rpcc in the >correct way. >How can I let the rpcc to get cycles when the dependency register has been >ready? Can you >give me a suggestion? > >Thanks! > >Richard R. Zhang >2006-05-17 > > > > > > >------------------------------------------------------- >Using Tomcat but need to do more? Need to support web services, security? >Get stuff done quickly with pre-integrated technology to make your job easier >Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo >http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 >_______________________________________________ >m5sim-users mailing list >[email protected] >https://lists.sourceforge.net/lists/listinfo/m5sim-users > > > ------------------------------------------------------- All the advantages of Linux Managed Hosting--Without the Cost and Risk! Fully trained technicians. The highest number of Red Hat certifications in the hosting industry. Fanatical Support. Click to learn more http://sel.as-us.falkag.net/sel?cmd=lnk&kid=107521&bid=248729&dat=121642 _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
