I'm guessing it's executing those few thousand instructions in the first
few milliseconds of your simulation and then getting stuck for some
reason. Can you turn on the InstExec trace flag and look at the output?
I'm expecting either it will just stop (deadlock) or get into a
repetitive pattern (livelock).
Steve
Bushra Ahsan wrote:
Hi,
Following is my run.py. When using mesa on all 4 CPUs, the number of
instructions simulated by each CPU is as follows ( simulation completed
in seconds for 50,000 instructions)
cpu0.num_insts 50000
cpu1.num_insts 49998
cpu2.num_insts 49997
cpu3.num_insts 49999
When using the mix ammp art equake mesa, the simulation did not get
completed even after a whole day for the same number of instructions and
after killing it, the statistics were as follows.
cpu0.num_insts 6500
cpu1.num_insts 17319
cpu2.num_insts 6833
cpu3.num_insts 7755
What could be the reason of the simulation getting stuck when using four
different benchmarks?
Please advice,
#################################################################
import Benchmarks
from MemConfig import *
from FuncUnitConfig import *
from DetailedUniConfig import *
## Memory Configuration#################################
## L1Cache configuration ###########
class BaseL1Cache(BaseCache):
size = '32kB'
assoc = 1
block_size = 32
mshrs = 4
tgts_per_mshr = 8
class IL1(BaseL1Cache):
latency = Parent.clock.period
mshrs = 8
write_buffers = 0
class DL1(BaseL1Cache):
latency = 1 * Parent.clock.period
mshrs = 32
write_buffers = 8
## L2Cache configuration ###########
class ToL2Bus(Bus):
width = 64
clock = Parent.clock.period
class L2(BaseCache):
size = '4MB'
assoc = '8'
block_size = 64
latency = 14 * Parent.clock.period
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
class ToMemBus(Bus):
width = 16
clock = 1 * Parent.clock.period
class SDRAM(BaseMemory):
latency = 100 * Parent.clock.period
uncacheable_latency = 1 * Parent.clock.period
## CPU Configuration #################################################
class CPU(SimpleCPU):
icache = IL1(out_bus=Parent.toL2bus)
dcache = DL1(out_bus=Parent.toL2bus)
## system configuration ########
class Simple_CMP(Root):
Coherence = CoherenceProtocol(protocol='msi')
cpu0 = CPU()
cpu1 = CPU()
cpu2 = CPU()
cpu3 = CPU()
cpu0.workload = Benchmarks.ammp()
cpu0.max_insts_any_thread = 50000
cpu1.workload = Benchmarks.art()
cpu1.max_insts_any_thread = 50000
cpu2.workload = Benchmarks.equake()
cpu2.max_insts_any_thread = 50000
cpu3.workload = Benchmarks.mesa()
cpu3.max_insts_any_thread = 50000
l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toMembus)
toMembus = ToMemBus()
sdram = SDRAM(in_bus=Parent.toMembus)
toL2bus = ToL2Bus()
hier = HierParams(do_data=False, do_events=True)
root = Simple_CMP()
Bushra Ahsan
PhD Student
Department of Electrical Engineering
City College at City University of New York
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