when using this command(dev/null) the simulation exits with the following number of instructions simulated ( in seconds) . I was using the run.py with four different benchmarks on each core

cpu0.num_insts                                   6635  
cpu1.num_insts                                  17870
cpu2.num_insts                                   7023
cpu3.num_insts                                   8075   

What could be causing the early exit or the deadlocks,
Thank you for the help,
Sincerely,

Bushra Ahsan

Steve Reinhardt <[EMAIL PROTECTED]> wrote:
The input file is specified with the 'input' parameter to the process
object (e.g., Benchmarks.ammp). But if they complete successfully when
run individually then I assume you are setting this correctly. Where
did you get your Benchmarks.py with the SPEC benchmarks in it?

On the other hand, I can't imagine why typing ctrl-d would do anything
to the simulation unless it is waiting for some input, which it wouldn't
be unless your benchmarks are trying to read from stdin. Are you doing
any input redirection on the command line? What happens if you take
your m5 command line and add '< /dev/null' to the end of it?

Steve

Bushra Ahsan wrote:
> Hello,
>
> Yes, I have run them individually and they complete normally. It is just
> four different benchmarks on different CPUs that is causing the deadlock.
> What can I do to fix this and how can I give the input.
>
> Thank you for the suggestions,
>
> Bushra Ahsan
>
>
>
>
> */Steve Reinhardt /* wrote:
>
> If typing ctrl-d makes it start up again, it sounds like the
> applications are waiting for input. Have you run each of these
> benchmarks individually (one copy of one benchmark on a single-cpu
> system)?
>
> Bushra Ahsan wrote:
> > Hi,
> >
> > I have tried the simulation without the caches. The simulation
> for four
> > different applications encounters deadlock even without caches.
> >
> > The simulation proceeds normally, then gets stuck. Hitting Ctrl D
> > resumes the simulation for a while and then it gets stuck again.
> Four or
> > five times the simulation gets resumed and then exits.
> >
> > Please Advice,
> >
> > Bushra Ahsan
> >
> >
> >
> > */Steve Reinhardt /* wrote:
> >
> > That confirms what I suspected... the CPUs stop simulating very
> > early on
> > and the whole thing just deadlocks. It's not clear why that's
> happening
> > though.
> >
> > What happens if you run the same multi-benchmark workload without
> > caches?
> >
> > Bushra Ahsan wrote:
> > > Hi,
> > >
> > > Turning on the InstExec flag shows that the simulation stops after
> > > running for a while when using the four different benchmarks.
> > Simulation
> > > proceeds normally and is completed when using the same
> benchmark (eg
> > > mesa) on all the four CPUs. What could possibly be causing the
> > deadlock.
> > > The last few instructions on which the simulation stops are as
> > follows
> > >
> > >
> > > 68543: cpu0 T0 : @__libc_read+16 : bne r1,0x12006c0d4 : IntAlu :
> > > 68544: cpu0 T0 : @__libc_read+20 : lda r0,3(r31) : IntAlu
> > > : D=0x0000000000000003
> > > 68544: cpu1 T0 : @tg_gen_con+140 : cmpult r1,r2,r28 : IntAlu
> > > : D=0x0000000000000001
> > > 68545: cpu1 T0 : @tg_gen_con+144 : blt r1,0x1200221e8 : IntAlu :
> > >
> > > The simulation gets stuck after this.
> > > Thank you for any suggestions,
> > >
> > > Bushra Ahsan
> > >
> > >
> > > */Steve Reinhardt /* wrote:
> > >
> > > I'm guessing it's executing those few thousand instructions in the
> > > first
> > > few milliseconds of your simulation and then getting stuck for some
> > > reason. Can you turn on the InstExec trace flag and look at the
> > output?
> > > I'm expecting either it will just stop (deadlock) or get into a
> > > repetitive pattern (livelock).
> > >
> > > Steve
> > >
> > > Bushra Ahsan wrote:
> > > > Hi,
> > > >
> > > > Following is my run.py. When using mesa on all 4 CPUs, the
> > number of
> > > > instructions simulated by each CPU is as follows ( simulation
> > > completed
> > > > in seconds for 50,000 instructions)
> > > >
> > > > cpu0.num_insts 50000
> > > > cpu1.num_insts 49998
> > > > cpu2.num_insts 49997
> > > > cpu3.num_insts 49999
> > > >
> > > >
> > > > When using the mix ammp art equake mesa, the simulation did
> not get
> > > > completed even after a whole day for the same number of
> > > instructions and
> > > > after killing it, the statistics were as follows.
> > > > cpu0.num_insts 6500
> > > > cpu1.num_insts 17319
> > > > cpu2.num_insts 6833
> > > > cpu3.num_insts 7755
> > > >
> > > > What could be the reason of the simulation getting stuck when
> > > using four
> > > > different benchmarks?
> > > >
> > > > Please advice,
> > > >
> > > >
> > > > #################################################################
> > > > import Benchmarks
> > > > from MemConfig import *
> > > > from FuncUnitConfig import *
> > > > from DetailedUniConfig import *
> > > >
> > > > ## Memory Configuration#################################
> > > > ## L1Cache configuration ###########
> > > >
> > > > class BaseL1Cache(BaseCache):
> > > > size = '32kB'
> > > > assoc = 1
> > > > block_size = 32
> > > > mshrs = 4
> > > > tgts_per_mshr = 8
> > > >
> > > > class IL1(BaseL1Cache):
> > > > latency = Parent.clock.period
> > > > mshrs = 8
> > > > write_buffers = 0
> > > >
> > > > class DL1(BaseL1Cache):
> > > > latency = 1 * Parent.clock.period
> > > > mshrs = 32
> > > > write_buffers = 8
> > > >
> > > >
> > > > ## L2Cache configuration ###########
> > > >
> > > > class ToL2Bus(Bus):
> > > > width = 64
> > > > clock = Parent.clock.period
> > > > class L2(BaseCache):
> > > > size = '4MB'
> > > > assoc = '8'
> > > > block_size = 64
> > > > latency = 14 * Parent.clock.period
> > > > mshrs = 92
> > > > tgts_per_mshr = 16
> > > > write_buffers = 8
> > > >
> > > > class ToMemBus(Bus):
> > > > width = 16
> > > > clock = 1 * Parent.clock.period
> > > >
> > > > class SDRAM(BaseMemory):
> > > > latency = 100 * Parent.clock.period
> > > > uncacheable_latency = 1 * Parent.clock.period
> > > >
> > > > ## CPU Configuration
> > > #################################################
> > > >
> > > > class CPU(SimpleCPU):
> > > > icache = IL1(out_bus=Parent.toL2bus)
> > > > dcache = DL1(out_bus=Parent.toL2bus)
> > > >
> > > > ## system configuration ########
> > > >
> > > > class Simple_CMP(Root):
> > > > Coherence = CoherenceProtocol(protocol='msi')
> > > >
> > > > cpu0 = CPU()
> > > > cpu1 = CPU()
> > > > cpu2 = CPU()
> > > > cpu3 = CPU()
> > > >
> > > > cpu0.workload = Benchmarks.ammp()
> > > > cpu0.max_insts_any_thread = 50000
> > > > cpu1.workload = Benchmarks.art()
> > > > cpu1.max_insts_any_thread = 50000
> > > > cpu2.workload = Benchmarks.equake()
> > > > cpu2.max_insts_any_thread = 50000
> > > > cpu3.workload = Benchmarks.mesa()
> > > > cpu3.max_insts_any_thread = 50000
> > > >
> > > > l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toMembus)
> > > > toMembus = ToMemBus()
> > > > sdram = SDRAM(in_bus=Parent.toMembus)
> > > > toL2bus = ToL2Bus()
> > > > hier = HierParams(do_data=False, do_events=True)
> > > >
> > > > root = Simple_CMP()
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > Bushra Ahsan
> > > > PhD Student
> > > > Department of Electrical Engineering
> > > > City College at City University of New York
> > > >
> > > >
> > >
> >
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> > > City College at City University of New York
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> > Department of Electrical Engineering
> > City College at City University of New York
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> Bushra Ahsan
> PhD Student
> Department of Electrical Engineering
> City College at City University of New York
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Department of Electrical Engineering
City College at City University of New York


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