I mean split per-cpu. and yes I meant coherence. Quoting Steve Reinhardt <[EMAIL PROTECTED]>:
> When you say "split", do you mean split I/D or split per-CPU? > > Also, I'm not sure what you mean by "synchronization": are you talking > about coherence? > > Finally, please post m5 questions to the m5-users mailing list rather > than sending them directly to me. > > Steve > > Forum Mangal Parmar wrote: > > Hi Steve, > > > > I am trying to understand the way the split cache implementation. > > > > I had one very specific question about m5 1.0. If I want to make the L2 > > split instead of shared in a multicore situation my question is: > > > > > > 1. Is it sufficient to make a .py file with each cpu having a L1 and L2 > > cache (ie declare the L2 cache in a similar way to L1) and then > replicate > > multiple cpus. In this case I will just replicate the L1 to get the L2 > and > > make one-to-one bus connections between every L1 and L2 and the next > level > > will be a shared L3 just delared in the same way as L2 is currently. > > > > or > > > > 2. Do I need to change the c++ code for synchronization of the split > caches? > > (ie do something like what is done in m5 2.0) > > > > Thank you, > > Forum > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
