Hi, I would like to instantiate multiple cores and still have control over the internals of the processors and the communication between them. Basically what I want to do is to define a higher level module that has r/w access to processor modules, so that we can accurately model the system we are investigating.
For example, I would like to modify the fetch stage so that each processor is running successive instructions of the same program. So say proc0 is running instructions 0,2,4,6... and proc1 is running instructions 1,3,5,7... Do you have any advice on how to implement this? Thanks, Christopher _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
