I would like to instantiate multiple cores and still have control over the internals of the processors and the communication between them. Basically what I want to do is to define a higher level module that has r/w access to processor modules, so that we can accurately model the system we are investigating.
You can do that, you're going to have to hack on the models to expose what you want though.
For example, I would like to modify the fetch stage so that each processor is running successive instructions of the same program. So say proc0 is running instructions 0,2,4,6... and proc1 is running instructions 1,3,5,7... Do you have any advice on how to implement this?
This would probably involve some major changes to the fetch stage, and probably the decode stage and the register file as well. I imagine that you're going to want dependencies between instructions on the different cores, and to pass information between the cores. Are you trying to do something where you can take two normal cores, but turn them into a cluster for higher performance?
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