Hey all,
Thanks to your great support, I modified the ISA and enabled
hardware-created multi-threads in SE mode.
I am now trying to add a separate scheduler unit into the simulator. A
control cpu sends command to the scheduler, and the scheduler sends commands
to other slave cpus.
With this infrastructure, I want to connect the scheduler and the cpus with
ports and buses. I have the following question:
1. I'm a little fuzzy on the mechanism of the "boilerplate"
macros(builder.hh) and how to use them. Does each parameter declared by the
macro correspond to a python class member? If so, why some python class
members don't appear in the corresponding C++ class member list? ( for
example, _mem_ports, icache, dcache are declared in BaseCPU.py, but there
are no corresponding members in the C++ class.) Moreover, icache_port,
dcache_port are also declared in BaseCPU.py and although they have
correspondence in AtomicSimpleCPU (icachePort, dcachePort), these parameters
are not declared by the macros in atomic.cc . Can you elaborate on the
rules? Thanks!
2. I wonder how I can connect the scheduler with the cpus. I see how
the python scripts connect different units by assigning ports. ( in
BaseCPU.py:
def addPrivateSplitL1Caches(self, ic, dc):
assert(len(self._mem_ports) == 2)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
but how are these ports' C++ correspondences get connected? What do I need
to do so that I can write similar things such as:
===in MySlaveCPU.py===
def connectScheduler(self, bus):
self.sched_port = bus.port
===in MyTest.py===
scheduler.slave_side = bus.port
scheduler.control_side = control_cpu.sched_port
Thanks again!
Jiayuan
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