A big applause :) very helpful, I'm gonna take try ... Just curious, when is the estimated release time of 2.0 final?
Appreciate it! -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Steve Reinhardt Sent: Friday, May 25, 2007 4:34 PM To: M5 users mailing list Subject: Re: [m5-users] port connection and macros Sorry we didn't respond to this sooner... I was traveling, but I'm not sure what everyone else's excuses are :-). Jiayuan wrote: > Hey all, > > > > Thanks to your great support, I modified the ISA and enabled > hardware-created multi-threads in SE mode. > > > > I am now trying to add a separate scheduler unit into the simulator. A > control cpu sends command to the scheduler, and the scheduler sends > commands to other slave cpus. > > > > With this infrastructure, I want to connect the scheduler and the cpus > with ports and buses. I have the following question: > > > > 1. I'm a little fuzzy on the mechanism of the "boilerplate" > macros(builder.hh) and how to use them. Does each parameter > declared by the macro correspond to a python class member? If so, > why some python class members don't appear in the corresponding > C++ class member list? ( for example, _/mem/_ports, icache, dcache > are declared in BaseCPU.py, but there are no corresponding members > in the C++ class.) Moreover, icache_port, dcache_port are also > declared in BaseCPU.py and although they have correspondence in > AtomicSimpleCPU (icachePort, dcachePort), these parameters are not > declared by the macros in atomic.cc . Can you elaborate on the > rules? Thanks! This is pretty gnarly code... basically all of the python parameters *except* the ports should also be declared using the builder.hh macros. The ports are handled through a different mechanism, where the SimObject maps names to Port objects via its getPort() method. The corresponding ports then get hooked up at runtime when the Python calls connectPorts() (in src/python/swig/pyobject.cc in 2.0b3, though I think it used to be in src/sim/main.cc in 2.0b2 and earlier). Just as a heads up, all the builder.hh macros will be going away by 2.0 final; we'll be auto-generating the C++ from the python directly so we won't have redundant specifications in both languages. > 2. I wonder how I can connect the scheduler with the cpus. I see how > the python scripts connect different units by assigning ports. ( > in BaseCPU.py: > > def addPrivateSplitL1Caches(self, ic, dc): > > assert(len(self._mem_ports) == 2) > > self.icache = ic > > self.dcache = dc > > self.icache_port = ic.cpu_side > > self.dcache_port = dc.cpu_side > > self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] > > > > but how are these ports' C++ correspondences get connected? What do I > need to do so that I can write similar things such as: > > > > ===in MySlaveCPU.py=== > > def connectScheduler(self, bus): > > self.sched_port = bus.port > > ===in MyTest.py=== > > scheduler.slave_side = bus.port > > scheduler.control_side = control_cpu.sched_port > > I hope my answer above addresses that. However I'm not sure you want to use this mechanism; it's designed for hooking up memory objects (caches, busses, memory, CPU memory ports, etc.)---things that communicate memory requests via Packet objects---and not SimObjects in general. If you're not trying to simulate a memory-mapped interface, you probably just want to declare SimObject parameters so that your scheduler gets pointers to the things it wants to talk to. Then you can define your own C++ methods to define that interface. For example, in Scheduler.py: class Scheduler(SimObject): control_cpu = Param.BaseCPU("control cpu") slave_cpus = VectorParam.BaseCPU("slave cpus") and then use SimObjectParam<BaseCPU*> and SimObjectVectorParam<BaseCPU*> in the C++ boilerplate code. Steve _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
