Hey all,
When tracking cache write accesses for the second level shared cache for a CMP
architecture, I found that there is no write access to it (# demand accesses =
# readreq accesses). However, the L1 level Dcaches have write misses. The first
write to any data must result in a miss in the L2. So I am very much confused.
I followed the output of the m5v2.0 beta3's built-in statistics printed out in
m5stats.txt. My system config is a CMP structure with private L1 Icaches and
Dcaches, and a shared L2. The coherence protocol is moesi.
Thanks for any help!
Jiayuuan
========== attached stats for l2 =======
system.l2.ReadExReq_accesses 12651 #
number of ReadExReq accesses(hits+misses)
system.l2.ReadExReq_avg_miss_latency 14000.972526 #
average ReadExReq miss latency
system.l2.ReadExReq_avg_mshr_miss_latency 11000 #
average ReadExReq mshr miss latency
system.l2.ReadExReq_hits 8538 #
number of ReadExReq hits
system.l2.ReadExReq_miss_latency 57586000 #
number of ReadExReq miss cycles
system.l2.ReadExReq_miss_rate 0.325113 #
miss rate for ReadExReq accesses
system.l2.ReadExReq_misses 4113 #
number of ReadExReq misses
system.l2.ReadExReq_mshr_miss_latency 45243000 #
number of ReadExReq MSHR miss cycles
system.l2.ReadExReq_mshr_miss_rate 0.325113 #
mshr miss rate for ReadExReq accesses
system.l2.ReadExReq_mshr_misses 4113 #
number of ReadExReq MSHR misses
system.l2.ReadReq_accesses 1389036 #
number of ReadReq accesses(hits+misses)
system.l2.ReadReq_avg_miss_latency 14001.262626 #
average ReadReq miss latency
system.l2.ReadReq_avg_mshr_miss_latency 10998.421717 #
average ReadReq mshr miss latency
system.l2.ReadReq_hits 1385868 #
number of ReadReq hits
system.l2.ReadReq_miss_latency 44356000 #
number of ReadReq miss cycles
system.l2.ReadReq_miss_rate 0.002281 #
miss rate for ReadReq accesses
system.l2.ReadReq_misses 3168 #
number of ReadReq misses
system.l2.ReadReq_mshr_miss_latency 34843000 #
number of ReadReq MSHR miss cycles
system.l2.ReadReq_mshr_miss_rate 0.002281 #
mshr miss rate for ReadReq accesses
system.l2.ReadReq_mshr_misses 3168 #
number of ReadReq MSHR misses
system.l2.Writeback_accesses 16805 #
number of Writeback accesses(hits+misses)
system.l2.Writeback_hits 16805 #
number of Writeback hits
system.l2.avg_blocked_cycles::no_mshrs no value #
average number of cycles each access was blocked
system.l2.avg_blocked_cycles::no_targets no value #
average number of cycles each access was blocked
system.l2.avg_refs no value #
Average number of references to valid blocks.
system.l2.blocked::no_mshrs 0 #
number of cycles access was blocked
system.l2.blocked::no_targets 0 #
number of cycles access was blocked
system.l2.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
system.l2.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.l2.cache_copies 0 #
number of cache copies performed
system.l2.demand_accesses 1389036 #
number of demand (read+write) accesses
system.l2.demand_avg_miss_latency 14001.262626 #
average overall miss latency
system.l2.demand_avg_mshr_miss_latency 10998.421717 #
average overall mshr miss latency
system.l2.demand_hits 1385868 #
number of demand (read+write) hits
system.l2.demand_miss_latency 44356000 #
number of demand (read+write) miss cycles
system.l2.demand_miss_rate 0.002281 #
miss rate for demand accesses
system.l2.demand_misses 3168 #
number of demand (read+write) misses
system.l2.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
system.l2.demand_mshr_miss_latency 34843000 #
number of demand (read+write) MSHR miss cycles
system.l2.demand_mshr_miss_rate 0.002281 #
mshr miss rate for demand accesses
system.l2.demand_mshr_misses 3168 #
number of demand (read+write) MSHR misses
system.l2.fast_writes 0 #
number of fast writes performed
system.l2.mshr_cap_events 0 #
number of times MSHR cap was activated
system.l2.no_allocate_misses 0 #
Number of misses that were no-allocate
system.l2.overall_accesses 1405841 #
number of overall (read+write) accesses
system.l2.overall_avg_miss_latency 14001.262626 #
average overall miss latency
system.l2.overall_avg_mshr_miss_latency 10998.421717 #
average overall mshr miss latency
system.l2.overall_avg_mshr_uncacheable_latency no value
# average overall mshr uncacheable latency
system.l2.overall_hits 1402673 #
number of overall hits
system.l2.overall_miss_latency 44356000 #
number of overall miss cycles
system.l2.overall_miss_rate 0.002253 #
miss rate for overall accesses
system.l2.overall_misses 3168 #
number of overall misses
system.l2.overall_mshr_hits 0 #
number of overall MSHR hits
system.l2.overall_mshr_miss_latency 34843000 #
number of overall MSHR miss cycles
system.l2.overall_mshr_miss_rate 0.002253 #
mshr miss rate for overall accesses
system.l2.overall_mshr_misses 3168 #
number of overall MSHR misses
system.l2.overall_mshr_uncacheable_latency 0 #
number of overall MSHR uncacheable cycles
system.l2.overall_mshr_uncacheable_misses 0 #
number of overall MSHR uncacheable misses
system.l2.prefetcher.num_hwpf_already_in_cache 0
# number of hwpf that were already in the cache
system.l2.prefetcher.num_hwpf_already_in_mshr 0
# number of hwpf that were already in mshr
system.l2.prefetcher.num_hwpf_already_in_prefetcher 0
# number of hwpf that were already in the pre
system.l2.prefetcher.num_hwpf_evicted 0 #
number of hwpf removed due to no buffer left
system.l2.prefetcher.num_hwpf_identified 0 #
number of hwpf identified
system.l2.prefetcher.num_hwpf_issued 0 #
number of hwpf issued
system.l2.prefetcher.num_hwpf_removed_MSHR_hit 0
# number of hwpf removed because MSHR allocated
system.l2.prefetcher.num_hwpf_span_page 0 #
number of hwpf spanning a virtual page
system.l2.prefetcher.num_hwpf_squashed_from_miss 0
# number of hwpf that got squashed due to a miss_______________________________________________
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