M5 does not provide any general network models out of the box; our
only interconnect model at this point is a split-transaction bus
(which you can combine with caches and bus bridges to make fairly
complex hierarchies).

If you are interested in writing your own network models M5 would
provide a good substrate though.  We've recently updated our memory
system so that the caches and busses use a generic "port" model for
interconnection, so at the lowest level it would be easy to rip out a
bus and replace it with a network model of your choosing.

Our current cache coherence protocol relies on bus broadcast, so if
you want to do cache coherence across the network that would be
additional work.

Steve

On 11/6/07, Igor Andjelkovic <[EMAIL PROTECTED]> wrote:
> Hi,
>
> I am also a student who is interested in this topic.
> Can anyone answer, please.
>
> Igor
>
>
> Tony Frank <[EMAIL PROTECTED]> wrote:
>  Hi ,
>
> I am a graduate student who is doing research work on Network-on-chip for
> multi-core computer.
>
> I need a simulator that can do simulation for network-on-chip with different
>  topology, routing algorithm, router architecture, or different bus
> topology.
>
> I also need to implement some blocks or units to the network-on-chip so that
> I
>  can verify that my optimization design on the network-on-chip can improve
>  performnce , power consumption and reliability, scalability.
>
> I also expect the simulator can generate the detailed information about
>  cycle-accurate, packet-level bus behavior.
>
> I found  "m5" simulator here.
>
> I do not know weather it can give me what I need.
>
> Would you please help me with it ?
>
> Or could you please recommmand other simulator for Network-on-chip?
>
> thanks a lot !!!
>
> Tony
>
> Oct.  25  2007
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