I just mean that as far as ethernet goes, we have point-to-point
links, but no way to hook up more than two systems on a LAN.  You'd
have to make a model for an ethernet switch to hook up more than two
systems.

This is true in both 2.0b3 and 2.0b4.

Steve

On 11/6/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> Sounds very good. What do you mean by "we just have"?
> I am using M5 2.0b3. Is that ok?
>
> Xin
>
> ---- Original message ----
> >Date: Tue, 6 Nov 2007 19:08:11 -0800
> >From: "Steve Reinhardt" <[EMAIL PROTECTED]>
> >Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
> >To: "M5 users mailing list" <m5-users@m5sim.org>
> >
> >M5 models ethernet connections between machines, so if you want to
> >model a cluster-type system you're in good shape (though we just have
> >point-to-point links, so you'd need to write an ethernet switch model,
> >but that shouldn't be too hard).
> >
> >My previous email was referring to on-chip networks, where you're
> >presumably connecting CPUs and caches within a single system.
> >
> >Steve
> >
> >On 11/6/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> >> Does M5 provide the message passing communication over
> >> the network? Can I have several machines(each has its cpu and
> >> memory) work together with data transfers among them?
> >>
> >> Xin
> >>
> >> ---- Original message ----
> >> >Date: Tue, 6 Nov 2007 15:58:04 -0800
> >> >From: "Steve Reinhardt" <[EMAIL PROTECTED]>
> >> >Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
> >> >To: "M5 users mailing list" <m5-users@m5sim.org>
> >> >
> >> >M5 does not provide any general network models out of the box; our
> >> >only interconnect model at this point is a split-transaction bus
> >> >(which you can combine with caches and bus bridges to make fairly
> >> >complex hierarchies).
> >> >
> >> >If you are interested in writing your own network models M5 would
> >> >provide a good substrate though.  We've recently updated our memory
> >> >system so that the caches and busses use a generic "port" model for
> >> >interconnection, so at the lowest level it would be easy to rip out a
> >> >bus and replace it with a network model of your choosing.
> >> >
> >> >Our current cache coherence protocol relies on bus broadcast, so if
> >> >you want to do cache coherence across the network that would be
> >> >additional work.
> >> >
> >> >Steve
> >> >
> >> >On 11/6/07, Igor Andjelkovic <[EMAIL PROTECTED]> wrote:
> >> >> Hi,
> >> >>
> >> >> I am also a student who is interested in this topic.
> >> >> Can anyone answer, please.
> >> >>
> >> >> Igor
> >> >>
> >> >>
> >> >> Tony Frank <[EMAIL PROTECTED]> wrote:
> >> >>  Hi ,
> >> >>
> >> >> I am a graduate student who is doing research work on Network-on-chip 
> >> >> for
> >> >> multi-core computer.
> >> >>
> >> >> I need a simulator that can do simulation for network-on-chip with 
> >> >> different
> >> >>  topology, routing algorithm, router architecture, or different bus
> >> >> topology.
> >> >>
> >> >> I also need to implement some blocks or units to the network-on-chip so 
> >> >> that
> >> >> I
> >> >>  can verify that my optimization design on the network-on-chip can 
> >> >> improve
> >> >>  performnce , power consumption and reliability, scalability.
> >> >>
> >> >> I also expect the simulator can generate the detailed information about
> >> >>  cycle-accurate, packet-level bus behavior.
> >> >>
> >> >> I found  "m5" simulator here.
> >> >>
> >> >> I do not know weather it can give me what I need.
> >> >>
> >> >> Would you please help me with it ?
> >> >>
> >> >> Or could you please recommmand other simulator for Network-on-chip?
> >> >>
> >> >> thanks a lot !!!
> >> >>
> >> >> Tony
> >> >>
> >> >> Oct.  25  2007
> >> >>  __________________________________________________
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> >> >>
> >> >>
> >> >>
> >> >>  __________________________________________________
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> >> >>
> >> >_______________________________________________
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